Vertically Stacked FET Structure With Strained Channel Junction Control
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Solution Overview
Problem
The challenge in semiconductor device fabrication is to create transistors with shallow source/drain junctions to prevent lateral diffusion of dopants, which contributes to leakage currents and poor breakdown performance, while maintaining high-speed and reduced parasitic junction capacitance.
Innovation Solution
The implementation of a vertically stacked semiconductor device with a strained channel, utilizing a flipped upper semiconductor device that includes a stressed dielectric layer to impart intrinsic strain within the channel region, combined with a metallization layer interconnect and a backside residual SOI layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar transistors are used, then manufacturing is simpler, but leakage currents increase and breakdown performance deteriorates due to deep source/drain junctions
Solution Approach 1:
The patent transitions from planar transistors to vertically stacked transistors, moving the device structure into the third dimension. This vertical stacking enables shallow source/drain junctions while maintaining effective channel control, thereby improving breakdown performance and reducing leakage currents without sacrificing manufacturing feasibility
Solution Approach 2:
The vertically stacked transistor structure segments the channel into multiple vertical sections, allowing independent optimization of source/drain junction depths. This segmentation enables shallower junctions that prevent lateral dopant diffusion while maintaining effective gate control over each channel segment
2Object-generated harmful factors
If shallow source/drain junctions are created to prevent lateral diffusion, then leakage currents are reduced, but manufacturing precision requirements increase
Solution Approach 1:
By transitioning to vertical stacking, the patent controls junction depth in the vertical dimension rather than relying solely on lateral precision. This dimensional shift allows shallower junctions with controlled vertical profiles, reducing lateral diffusion and leakage currents while managing manufacturing precision requirements through vertical epitaxial growth control
3Productivity
If vertically stacked structure with strained channel is implemented, then device performance is improved, but device complexity increases
Solution Approach 1:
The patent introduces strain as a controlled parameter in the channel region through the vertically stacked structure. By modifying the crystal lattice strain state through layered material composition and thickness control, carrier mobility is enhanced, improving device performance while managing structural complexity through systematic material parameter optimization
4Speed
If shallow junctions are used to reduce parasitic capacitance, then high-speed performance is achieved, but dopant diffusion control becomes more challenging
Solution Approach 1:
The vertical stacked structure controls dopant distribution primarily in the vertical dimension through epitaxial growth and ion implantation angles, rather than relying on lateral diffusion control. This enables shallow vertical junctions that reduce parasitic capacitance for high-speed operation while maintaining precise dopant placement and preventing unwanted lateral diffusion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high-performance transistors with shallow junctions, reducing leakage currents and improving breakdown performance by enhancing the strain within the channel region, thus achieving improved device performance and efficiency.
Implementation Method 1
a first stressed dielectric portion upon the backside residual SOI layer that imparts an intrinsic strain within the backside residual SOI layer
Data Source
AI summary
A stacked semiconductor device includes a lower semiconductor device that has a backside and includes a flipped upper semiconductor device that has a backside that is opposed to the lower semiconductor device backside. The flipped upper semiconductor device further includes a backside residual semiconductor on insulator (SOI) layer and a stressed dielectric portion thereupon. The stacked semiconductor device may be formed by stacking and bonding the flipped upper semiconductor device to the lower semiconductor device, removing one or more semiconductor on insulator (SOI) layers from the backside of the flipped upper semiconductor device while retaining an exposed backside residual SOI layer of the flipped upper semiconductor device, forming a stressed dielectric layer upon the exposed backside residual SOI layer, and patterning the stressed dielectric layer.