Stacked FET Switch for RF Linearity
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Solution Overview
Problem
RF switches in an on-state generate undesirable harmonics due to non-linear conductance, which interfere with RF transceiver receiver circuitry.
Innovation Solution
A stacked field-effect transistor (FET) switch is designed with a first FET device stack having decreasing conductance and a second FET device stack with increasing conductance as voltage increases, both within specific breakdown voltage ranges, to counteract non-linear harmonic distortion by coupling FET devices in series and using bias circuitry to adjust DC bias voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If an RF switch is closed to pass transmit signals, then signal transmission is enabled, but non-linear conductance generates undesirable harmonics that interfere with receiver circuitry
Solution Approach 1:
The RF switch is divided into multiple FET devices connected in series, forming separate stacks with different conductance characteristics. This segmentation allows each stack to contribute differently to the overall conductance behavior, enabling harmonic distortion cancellation while maintaining signal transmission capability.
Solution Approach 2:
The patent employs FET stacks with opposing conductance characteristics (one with decreasing conductance, another with increasing conductance) to counterbalance each other's non-linear effects. This anti-weight approach cancels out harmonic distortion generated by individual stacks, allowing the RF switch to transmit signals without generating harmful harmonics.
2Object-generated harmful factors
If linearity compensation is applied to prevent harmonic distortion, then harmonic generation is reduced, but device complexity increases
Solution Approach 1:
Multiple FET devices with different conductance characteristics are merged into integrated stacked configurations. This combining approach achieves linearity compensation and harmonic distortion reduction within a unified switch structure, avoiding the need for separate compensation circuits and reducing overall system complexity.
Solution Approach 2:
The patent utilizes FET devices with inherently different conductance parameters (decreasing versus increasing conductance with voltage) to achieve linearity compensation. By selecting devices with complementary electrical characteristics rather than adding complex compensation circuitry, the solution reduces device complexity while effectively limiting harmonic distortion.
Data Source
AI summary
A stacked field-effect transistor (FET) switch is disclosed. The stacked FET switch has a first FET device stack that is operable in an on-state and in an off-state and is made up of a first plurality of FET devices coupled in series between a first port and a second port, wherein the first FET device stack has a conductance that decreases with increasing voltage between the first port and the second port. The stacked FET switch also includes a second FET device stack that is operable in the on-state and in the off-state and is made up of a second plurality of FET devices coupled in series between the first port and the second port, wherein the second FET device stack has a conductance that increases with increasing voltage between the first port and the second port.