Vertically Stacked FETs in Trenches for Switch Density
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Solution Overview
Problem
Conventional CMOS technologies for fabricating switches using single-level poly layout on silicon on insulator (SOI) wafers are expensive and inefficient in terms of chip area usage.
Innovation Solution
The development of vertically stacked field effect transistors (FETs) with a lower gate structure, epitaxial material, and an upper gate structure, formed using a trench in a substrate material, where the epitaxial material is isolated from the substrate and sidewalls, and the upper gate is stacked vertically, allowing for increased switch density and reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional CMOS technologies with single-level poly layout on SOI wafers are used, then manufacturing process is established, but chip area usage is large and manufacturing cost is high
Solution Approach 1:
The patent transitions from conventional planar (2D) FET layout to vertically stacked (3D) FET configuration. By stacking multiple FETs vertically along the channel length direction, the design utilizes the third dimension to increase switch density without proportionally increasing chip area, effectively resolving the contradiction between area usage and productivity.
Solution Approach 2:
The patent implements nested structures where upper FETs are positioned directly above lower FETs within the same trench region. This nesting arrangement allows multiple active devices to occupy a compact vertical space, maximizing switch density while minimizing the horizontal footprint on the chip.
2Productivity
If vertically stacked FETs are implemented, then switch density increases and chip area usage reduces, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is divided into distinct segments: forming trenches in the substrate, depositing gate structures, filling with insulator material, and growing epitaxial layers. This segmentation of the complex manufacturing process into manageable steps reduces overall complexity while enabling the vertically stacked configuration.
Solution Approach 2:
The patent performs preliminary actions by pre-forming trenches and insulator structures before growing the epitaxial material and forming upper gate structures. This preliminary preparation simplifies subsequent manufacturing steps and reduces the complexity of creating the final stacked configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces chip area usage and manufacturing costs by nearly halving the size of switch-intensive integrated circuits and increasing switch density, while utilizing bulk silicon wafers instead of expensive SOI wafers.
Implementation Method 1
growing an epitaxial material from the exposed sidewalls of the trench and over the recessed insulator material and the lower gate structure
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked field effect transistors and methods of manufacture. The structure includes: at least one lower gate structure on a bottom of a trench formed in substrate material; insulator material partially filling trench and over the at least one lower gate structure; an epitaxial material on the insulator material and isolated from sidewalls of the trench; and at least one upper gate structure stacked vertically above the at least one lower gate structure and located on the epitaxial material.