Stacked FET and Vertical Diode Layout for CMOS Backside Integration
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Solution Overview
Problem
The integration of backside structures with stacked field effect transistors (FETs) and passive devices in complementary metal oxide semiconductor (CMOS) scaling is challenging.
Innovation Solution
A semiconductor structure is developed with a stacked transistor configuration, including a top transistor over a bottom transistor, a gate structure, and a passive device positioned laterally, with specific surface and channel alignments, and a method of formation involving multilayer stack processing and semiconductor growth to create a semiconductor mesa with opposite polarity regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If backside structures are integrated with stacked FETs and passive devices in CMOS scaling, then device functionality and integration density are improved, but manufacturing complexity and integration difficulty increase
Solution Approach 1:
The patent divides the semiconductor device into distinct regions: a first region containing the stacked FETs and a second region containing the passive devices. This spatial segmentation allows each region to be optimized independently while maintaining overall integration, resolving the contradiction between integration capability and integration difficulty.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional integration by stacking FETs vertically and positioning passive devices in a separate lateral region. This dimensional approach enables higher integration density without proportionally increasing manufacturing complexity, as each region can be processed with techniques appropriate to its specific requirements.
2Productivity
If stacked FETs are scaled down for continued CMOS scaling, then transistor density is improved, but integration with backside structures becomes more difficult
Solution Approach 1:
By segmenting the device into a first region for stacked FETs and a second region for passive devices, the patent enables independent optimization of each region. The stacked FET region can be scaled down to increase transistor density without being constrained by the integration requirements of passive devices, thus resolving the contradiction between density and integration difficulty.
Solution Approach 2:
The patent applies local quality by providing different structural configurations in different regions: the first region has the vertical stacked FET architecture optimized for high density, while the second region has passive devices with configurations optimized for their specific functions. This localized optimization allows scaled-down FETs to be integrated without compromising overall device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables further competitive scaling of stacked FETs and passive devices, forms high-quality junctions with reduced defects, and improves diode ideality by maximizing area-to-periphery ratio.
Implementation Method 1
doping the semiconductor to form a top passive region having a first polarity and lower passive region having a second polarity wherein the first polarity is opposite of the second polarity
Data Source
AI summary
A semiconductor structure has a logic region and a passive region. The logic region includes a vertically stacked top and bottom transistors in which the top transistor has a topmost channel, and the bottom transistor has a bottommost channel. The passive region includes a semiconductor mesa having a top surface co-planar or above a topmost channel of the top transistor and a bottom surface co-planar or below the bottommost channel of the bottom transistor.