Stacked FET Gate Layout With Selective Via Isolation
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Solution Overview
Problem
Stacking FETs with both merged and separated gates in a single layout involves complex fabrication processes, increasing costs and reducing yield.
Innovation Solution
A semiconductor device is fabricated with both separated-gate and merged-gate transistors by forming a conductive via through the top gate to contact the bottom transistor, using a dielectric liner to insulate the top gate from the via in separated-gate transistors and directly connecting the gates in merged-gate transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If both merged-gate and separated-gate transistors are implemented on a single device, then layout versatility is improved, but fabrication complexity increases
Solution Approach 1:
The patent applies local quality by making the dielectric liner presence optional and location-specific. In regions where separated gates are needed, a dielectric liner is formed in the conductive via to electrically isolate the top gate from the bottom gate. In regions where merged gates are needed, no dielectric liner is formed, allowing direct electrical connection. This localized differentiation enables both merged-gate and separated-gate transistors to coexist on a single device using the same fabrication流程, thereby improving layout versatility without significantly increasing fabrication complexity.
2Reliability
If a dielectric liner is added to isolate gates, then electrical insulation is improved, but manufacturing steps increase
Solution Approach 1:
The patent applies dynamics by making the dielectric liner formation conditional rather than static and universal. The fabrication process includes an optional step where a dielectric liner is formed in the conductive via only in specific regions where electrical isolation is required. The presence or absence of the dielectric liner is dynamically determined by the local circuit requirements, allowing the same fabrication process to accommodate both merged-gate and separated-gate configurations without requiring entirely separate manufacturing flows.
3Adaptability or versatility
If complex fabrication processes are used to achieve both merged and separated gates, then device functionality is improved, but production yield decreases
Solution Approach 1:
The patent applies universality by designing a single fabrication process that can produce both merged-gate and separated-gate transistors on the same device. The key is the optional dielectric liner step, which can be selectively applied or omitted in different regions. This universal approach eliminates the need for separate fabrication processes for different transistor types, thereby maintaining high device functionality while avoiding the yield losses associated with complex, multi-process fabrication sequences.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces complexity, and maintains electrical connectivity while minimizing parasitic capacitances, thereby improving yield and reducing costs.
Implementation Method 1
A dielectric liner between the conductive via and the top gate electrically insulates the top gate from the conductive via
Data Source
AI summary
Semiconductor devices and methods of forming the same include a bottom transistor having a bottom gate. A top transistor has a top gate above the bottom gate and is separated from the bottom transistor by a dielectric layer. A conductive via extends through the top gate and the dielectric layer to contact the bottom transistor. A dielectric liner between the conductive via and the top gate electrically insulates the top gate from the conductive via.