Stacked FET RF Switch Capacitance Tuning for Voltage Balancing
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Solution Overview
Problem
Stacked FET RF switches often fail to withstand expected voltages due to voltage distribution inequalities caused by small parasitic capacitances, leading to premature failure of the most heavily stressed transistor, which in turn causes a domino effect among other FETs.
Innovation Solution
Intentionally modifying the drain-source capacitance values of transistors in the stack to create significant differences, and adding discrete capacitive elements to internal nodes to tune the capacitances, thereby balancing the voltage distribution across the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If small parasitic capacitances are present in stacked FET RF switches, then the circuit structure remains simple, but voltage distribution becomes unequal causing premature failure
Solution Approach 1:
The patent applies asymmetry by intentionally creating unequal drain-source capacitance values among the stacked FETs. Specifically, at least one FET is designed with a different capacitance value than others to compensate for parasitic capacitances. This asymmetric design balances the voltage distribution across the stack, preventing any single FET from being over-stressed and failing prematurely, thereby resolving the contradiction between simple structure and reliable operation.
2Ease of manufacture
If drain-source capacitance values are made equal for all transistors, then manufacturing is simplified, but voltage distribution inequality occurs due to parasitic capacitances
Solution Approach 1:
The patent applies local quality by making specific FETs in the stack have different drain-source capacitance values tailored to their position and parasitic characteristics. Rather than uniformly matching all capacitances, the design selectively adjusts capacitance values at specific locations in the stack to achieve optimal voltage distribution. This localized differentiation maintains ease of manufacture while ensuring reliable voltage balancing across the entire stack.
3Reliability
If capacitance tuning is implemented to balance voltage distribution, then voltage withstand capacity increases, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the drain-source capacitance values of individual FETs in the stack. By adjusting these capacitance parameters, the voltage distribution across the stacked FETs is optimized to achieve balanced stress distribution. This parameter tuning enables the circuit to withstand higher voltages reliably while maintaining a relatively simple structure, as the capacitance values are determined during the transistor design and fabrication process rather than requiring additional external components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the variance of the voltage distribution across all transistors, enhancing the voltage withstand capacity of the RF switch and preventing premature failure, allowing the switch to approach or reach the theoretical maximum voltage for the constituent transistors.
Implementation Method 1
adding discrete capacitive elements to internal nodes to tune the capacitances, thereby balancing the voltage distribution across the transistors
Data Source
AI summary
An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.