3D Stacked FET Wafer Flipping for Vertical Height Control
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Solution Overview
Problem
The challenge lies in managing and fabricating increasingly tall vertical stacks of field effect transistors, particularly in multi-voltage schemes, where existing methods struggle to maintain control over the vertical stack height and handling becomes difficult.
Innovation Solution
A semiconductor device fabrication method involving flip and backside processing to form three-dimensional monolithically stacked FINFETs or NSFETs, utilizing a bottom gate first or top gate last transistor configuration, which allows for controlled vertical stack height and improved handling through a series of gate and source/drain region formations on both the frontside and backside of a wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical stacks of field effect transistors are made taller to increase device capacity, then the device can accommodate more transistors and provide higher computing power, but the vertical stack height becomes difficult to control and handling becomes difficult
Solution Approach 1:
The patent transitions from conventional planar transistor arrangements to three-dimensional vertically stacked transistor configurations. By stacking transistors in the vertical dimension, the device can accommodate more transistors (increasing quantity) while maintaining a compact footprint. The wrap-around gate structure extends control into the vertical dimension, enabling precise manufacturing control of tall stacks through enhanced electrostatic control and process techniques.
2Quantity of substance
If vertical stacks of field effect transistors are made taller to increase device capacity, then the device can accommodate more transistors and provide higher computing power, but handling becomes difficult
Solution Approach 1:
The patent divides the vertical stack into discrete, manageable transistor units, each with its own source, drain, and gate regions. This segmentation allows the stack to be constructed incrementally through sequential processing steps, making handling more manageable. The wrap-around gate structure provides modular control over each transistor segment, enabling precise manipulation and assembly of tall stacks during fabrication.
3Reliability
If wrap-around gate structure is used to control the channel, then electrical control over the channel is improved, but the fabrication process complexity increases
Solution Approach 1:
The patent employs preliminary actions in the fabrication process by first forming the semiconductor fins and isolation structures, then sequentially depositing and patterning gate materials in controlled steps. The wrap-around gate is constructed incrementally, with the gate electrode and dielectric layers being deposited and patterned in a predetermined sequence. This preliminary structuring simplifies the overall fabrication complexity by establishing a systematic process flow that builds the complex wrap-around gate structure through manageable, repeatable steps.
Data Source
AI summary
A semiconductor device fabrication method is provided. The semiconductor device fabrication method includes frontside semiconductor device processing on a frontside of a wafer, flipping the wafer, backside semiconductor device processing on a backside of the wafer and backside and frontside contact formation processing on the backside and frontside of the wafer, respectively.