Stacked FET Gate Dielectric Doping for Independent Work Function Control
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Solution Overview
Problem
Current manufacturing schemes struggle to selectively remove work function/threshold influencing materials from the upper gate metal layers in a 3D stacked transistor architecture, making it difficult to independently define a tailored work function for the upper transistor.
Innovation Solution
The semiconductor device employs a doped gate dielectric structure with a tailored work function dipole layer sequence and a sacrificial cap layer to selectively retain only the tuned dipole layer for the top device gate during fabrication, enabling independent work function control for the upper stacked transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a 3D stacked transistor architecture is used to maximize density, then the number of transistors per unit area increases, but it becomes difficult to independently define work function for upper transistors
Solution Approach 1:
The gate dielectric layer is segmented into multiple sections along the vertical axis, with each section having different doping concentrations. This allows independent work function engineering for upper and lower transistors within the stacked architecture, resolving the contradiction between high density and work function control.
Solution Approach 2:
Different regions of the gate dielectric are doped with different concentrations of dopant atoms, creating local variations in electrical properties. The upper portion has one doping concentration while the lower portion has another, enabling tailored work functions for each transistor level without compromising overall device density.
2Reliability
If work function materials are added to tailor threshold voltage, then transistor performance is improved, but the structure becomes more complex and harder to manufacture
Solution Approach 1:
Dopant atoms are incorporated into the gate dielectric layer during its formation process, before any work function materials are deposited. This preliminary doping action establishes the baseline work function for each transistor level, simplifying subsequent fabrication steps and reducing overall manufacturing complexity.
Solution Approach 2:
The work function is tuned by changing the doping concentration parameter in the gate dielectric layer rather than adding separate work function material layers. This parameter change approach maintains structural simplicity while achieving the desired electrical characteristics for high-performance transistors.
3Manufacturing precision
If the gate dielectric is doped to adjust work function, then work function control is improved, but the processing steps increase
Solution Approach 1:
The gate dielectric formation and doping steps are merged into a single integrated process. The dopant is incorporated during dielectric deposition, combining two processing operations into one, thereby achieving precise work function control without proportionally increasing the total number of processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reliable and repeatable engineering of a tailored work function for the upper stacked transistor, enabling multiple Vt devices in a monolithic 3D layout, which maximizes density and flexibility in designing complementary high-performance logic circuits.
Implementation Method 1
a first gate dielectric over a top surface and top-half of sidewalls of the isolation box, wherein second portions of the first gate dielectric encapsulate a first plurality of nanosheets in the top transistor, and wherein first portions of the first gate dielectric cover a top surface and top-half of sidewalls of the isolation box
Data Source
AI summary
A semiconductor device includes a top transistor, a bottom transistor, an isolation box between the top transistor and the bottom transistor, a first gate dielectric, and a second gate dielectric. First portions of the first gate dielectric cover a top surface and top-half of sidewalls of the isolation box, and first portions of the second gate dielectric cover a bottom surface and bottom-half of the sidewalls of the isolation box.