Stacked Low-Dimensional Fin Channels for Short-Channel Control
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Solution Overview
Problem
Current semiconductor transistor technologies face challenges in achieving high carrier mobility and reducing short-channel effects due to the limitations of traditional channel materials, particularly in the formation and integration of low-dimensional materials within existing fabrication processes.
Innovation Solution
The formation of transistors using low-dimensional materials such as carbon nanotube networks and Transition Metal Dichalcogenides (TMDs) as channel materials, which are stacked and patterned into a protruding fin structure, allowing for the creation of FinFET or Gate-All-Around transistors with improved carrier mobility and energy bandgap values, while maintaining compatibility with existing integrated circuit processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional channel materials are used in semiconductor transistors, then fabrication processes are simpler and more established, but carrier mobility is limited and short-channel effects increase
Solution Approach 1:
The patent changes the dimensional parameters of the channel material from traditional three-dimensional bulk materials to low-dimensional materials (2D, 1D, and 0D structures). This parameter change enables higher carrier mobility and better control of short-channel effects while maintaining compatibility with existing fabrication processes through adapted deposition and patterning techniques
Solution Approach 2:
The patent employs composite structures combining multiple low-dimensional material layers (e.g., alternating layers of semiconducting carbon nanotubes and insulating materials, or stacked 2D material layers) to achieve superior electrical properties. These composite low-dimensional channel structures provide both high carrier mobility and effective short-channel effect suppression
2Reliability
If low-dimensional materials are integrated into existing fabrication processes, then transistor performance improves, but process compatibility and integration difficulty increase
Solution Approach 1:
The patent segments the low-dimensional material channel into discrete, controllable layers and structures that can be independently formed and integrated. This segmentation allows each layer to be optimized separately and integrated into existing fabrication processes in a modular fashion, improving both performance and manufacturability
Solution Approach 2:
The patent introduces intermediary layers and structures (such as buffer layers, capping layers, and patterned masks) that facilitate the integration of low-dimensional materials with conventional fabrication processes. These intermediaries enable compatibility between the novel low-dimensional channel materials and existing manufacturing equipment and processes
Data Source
AI summary
A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.