Stacked Fin Structure Germanium Diffusion Barrier
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing fin field effect transistors (Fin FETs) with high aspect ratios, particularly in controlling carrier mobility and suppressing germanium diffusion, which affects device performance and reliability.
Innovation Solution
The process involves forming fin structures with a bottom portion of Si(1-x)Gex and an upper portion of Si or Si(1-y)Ge, embedding them in a sacrificial layer, and using a protective layer to prevent oxidation, followed by the growth of a third semiconductor layer as a channel region, with a gate structure formed over the channel regions to enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If germanium or silicon germanium is used as channel region to enhance carrier mobility, then carrier mobility is improved, but germanium diffusion occurs which affects device performance and reliability
Solution Approach 1:
A third semiconductor layer is introduced as an intermediary between the first semiconductor layer (SiGe) and the channel region. This intermediate layer acts as a diffusion barrier that prevents germanium atoms from migrating into the channel region while still allowing the beneficial carrier mobility enhancement from the SiGe layer to be maintained.
Solution Approach 2:
The semiconductor structure is divided into multiple distinct layers with different compositions and functions. The first semiconductor layer provides stress enhancement, the third semiconductor layer provides diffusion barrier functionality, and the channel region provides carrier transport. This segmentation allows each layer to perform its specific function without interfering with the others.
2Productivity
If fin structures with high aspect ratios are formed to increase device density, then device density is improved, but manufacturing precision becomes more difficult to control
Solution Approach 1:
The first and second semiconductor layers are formed and patterned into fin structures before the actual device fabrication process. This preliminary structuring establishes the high-aspect-ratio fin geometry early in the manufacturing process, allowing subsequent layers to be deposited conformally around these pre-formed structures, thereby maintaining manufacturing precision despite the high aspect ratio.
Solution Approach 2:
Multiple semiconductor layers are nested within each other to form the fin structure. The first semiconductor layer is positioned within the second semiconductor layer, creating a nested configuration that maintains structural integrity and dimensional control throughout the high-aspect-ratio fin structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves carrier mobility, suppresses germanium diffusion, and reduces current leakage, leading to more reliable and efficient Fin FET devices.
Implementation Method 1
The first semiconductor layer may be configured to provide stress enhancement to the third semiconductor layer channel region
Implementation Method 2
A cover layer is formed on a bottom part of the fin structure so as to cover side walls of the bottom portion of the fin structure and a bottom part of side walls of the upper portion of the fin structure
Implementation Method 3
a first semiconductor layer is formed on a substrate. A second semiconductor layer is formed on the first semiconductor layer
Data Source
AI summary
In manufacturing a semiconductor device, a stack of first and second semiconductor layers are formed. A fin structure is formed by patterning the first and second semiconductor layers. A cover layer is formed on a bottom part of the fin structure so as to cover side walls of the bottom portion of the fin structure and a bottom part of side walls of the upper portion of the fin structure. An insulating layer is formed so that the fin structure is embedded in the insulating layer. A part of the upper portion is removed so that an opening is formed in the insulating layer. A third semiconductor layer is formed in the opening on the remaining layer of the second semiconductor layer. The insulating layer is recessed so that a part of the third semiconductor layer is exposed from the insulating layer, and a gate structure is formed.