Stacked FinFET SRAM Bitcell With Angled Vertical Alignment
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Solution Overview
Problem
Current semiconductor device fabrication techniques for static random access memory (SRAM) devices lack improved structures that incorporate stacked field-effect transistors, which are essential for enhancing performance and efficiency in data storage and processing.
Innovation Solution
The proposed solution involves forming a structure with a bitcell that includes a first fin and a second fin arranged over the first fin, with a shared gate structure and source/drain regions, where the second fin is aligned at an angle relative to the first fin, allowing for the creation of vertically stacked field-effect transistors with shared gate and source/drain regions, facilitating efficient data storage and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional planar or fin-type field-effect transistor structures are used, then the device structure is simple and easy to manufacture, but the data storage and processing efficiency is limited
Solution Approach 1:
The patent transitions from traditional planar (2D) transistor structures to vertically stacked 3D transistor structures. Multiple fins are arranged in vertical stacks with shared gate structures, utilizing the third dimension (vertical direction) to increase transistor density and improve data storage efficiency without proportionally increasing manufacturing complexity
Solution Approach 2:
The patent combines multiple fins into stacked configurations where adjacent fins share common gate structures and source/drain regions. This merging approach allows multiple transistors to be integrated in a compact vertical space, improving productivity while managing device complexity through shared components
2Quantity of substance
If vertically stacked field-effect transistors with shared gate structures are implemented, then the data storage capacity increases, but the manufacturing precision requirements increase
Solution Approach 1:
The patent segments the transistor structure into distinct vertical layers (multiple fins stacked) with shared horizontal components (gates and source/drain regions). This segmentation allows independent optimization of vertical stacking for density while using shared horizontal structures to reduce precision requirements, as misalignments in one fin do not critically affect adjacent fins in the stack
3Reliability
If fins are arranged with angular alignment, then the overlapping arrangement with gate structure is improved, but the patterning complexity increases
Solution Approach 1:
The patent employs asymmetric fin arrangements where fins are oriented at specific angles (e.g., 45 degrees) relative to each other rather than parallel alignment. This asymmetric configuration optimizes the overlapping arrangement between fins and shared gate structures, improving electrical reliability while the angular pattern can be achieved through standard photolithography techniques
Data Source
AI summary
Structures that include stacked field-effect transistors and methods for forming a structure that includes stacked field-effect transistors. A structure includes a first fin, a second fin arranged over the first fin, a first dielectric layer between the first fin and the second fin, and a first inverter. The first inverter includes a first field-effect transistor with a channel region in the first fin and a second field-effect transistor with a channel region in the second fin. The first field-effect transistor and the second field-effect transistor share a first gate structure having an overlapping arrangement with the channel region in the first fin and the channel region in the second fin. The first fin has a longitudinal axis, and the second fin has a longitudinal axis that is aligned at an angle relative to the longitudinal axis of the first fin.