Stacked FinFETs with Self-Aligned Junction Isolation
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Solution Overview
Problem
Current semiconductor device manufacturing methods face challenges in efficiently forming stacked FinFETs with self-aligned junction isolation, particularly in achieving high mobility and low leakage current while avoiding complex lithography and etch processes.
Innovation Solution
The method involves cyclic epitaxial growth and implantation processes to form stacked FinFETs with self-aligned junction isolation, using multiple semiconductive materials with different doping types to create channel regions and source/drain regions, and patterning these using selective etch processes to form 3D stacked FinFET CMOS inverters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional lithography and etch processes are used to form stacked FinFETs, then device integration is achieved, but manufacturing complexity increases and alignment precision becomes difficult to maintain
Solution Approach 1:
The patent employs self-aligned epitaxial growth where the junction isolation regions are automatically positioned relative to the FinFET channels through the growth process itself, eliminating the need for separate lithography alignment steps. The semiconductor layers self-organize to create precisely positioned isolation regions without requiring complex photolithography patterning.
Solution Approach 2:
The patent replaces mechanical lithography and etch processes with a chemical epitaxial growth process. Instead of using lithography to define patterns and etch to remove material, the junction isolation regions are formed through in-situ semiconductor layer growth that automatically creates the desired structure with atomic-level precision.
2Manufacturing precision
If cyclic epitaxial growth and implantation processes are used to form stacked FinFETs, then manufacturing precision improves, but production time increases
Solution Approach 1:
The patent combines multiple process steps into a single cyclic epitaxial growth and implantation sequence. The growth of semiconductor layers and the implantation of dopants are integrated into alternating cycles within the same reactor, eliminating the need for separate processing chambers and reducing overall manufacturing time while maintaining precise junction isolation alignment.
Solution Approach 2:
The cyclic epitaxial growth and implantation processes operate continuously in an in-situ manner without breaking vacuum or moving wafers between chambers. Each cycle of layer growth followed by dopant implantation occurs seamlessly, maximizing equipment utilization and reducing cycle time compared to discrete batch processing.
3Reliability
If through-substrate via fabrication is avoided, then device reliability improves, but manufacturing versatility decreases
Solution Approach 1:
The patent transitions from planar FinFET structures to three-dimensional stacked FinFET configurations. By stacking multiple FinFET devices vertically, the design achieves higher integration density and improved electrical performance without requiring through-substrate vias, while the epitaxial growth process maintains flexibility for various device configurations.
Solution Approach 2:
The patent divides the semiconductor structure into multiple discrete layers formed through cyclic epitaxial growth. Each layer can be independently doped and positioned, allowing precise control over device characteristics and enabling various FinFET configurations (n-type, p-type, stacked arrangements) without requiring through-substrate connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in high-speed, low-voltage operation semiconductor devices with superior circuit performance, reduced leakage current, and simplified manufacturing that integrates additional FinFET devices, avoiding the need for through-substrate via fabrication and complex lithography alignment.
Implementation Method 1
cyclic epitaxial growth and implantation processes to form stacked FinFETs
Implementation Method 2
cyclic epitaxial growth and implantation processes to form stacked FinFETs
Implementation Method 3
patterning these using selective etch processes to form 3D stacked FinFET CMOS inverters
Data Source
AI summary
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first fin field effect transistor (FinFET) disposed over a substrate, and a second FinFET device disposed over the first FinFET. A junction isolation material is disposed between a source of the first FinFET and a source of the second FinFET.