Stacked FinFET SRAM Bitcell Layout for Area Reduction
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Solution Overview
Problem
Current SRAM architectures have large bitcell areas, which hinder the integration of a large number of memory cells on a chip while minimizing transistor resistance and capacitance, necessitating a reduction in memory cell size and increasing integration density.
Innovation Solution
The use of stacked n-type and p-type FinFETs with a novel 6T SRAM layout, featuring a 2 fin pitch and 3 gate pitch, along with optimized contact configurations and gate lengths, to reduce bitcell area and improve conduction and leakage control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional 6T SRAM architecture with 4 fin pitch and 3 gate pitch is used, then transistor conduction and leakage control is maintained, but bitcell area is large (12 unit2)
Solution Approach 1:
The patent transitions from a planar 2D layout to a 3D stacked configuration by forming FinFETs vertically over the substrate. The gate is wrapped around the fin structure, creating a three-dimensional conduction path that improves control while reducing the horizontal footprint of each bitcell from 12 unit2 to 8 unit2.
Solution Approach 2:
The gate structure is nested around the fin channel in a wrap-around configuration, with the gate enclosing the fin on multiple sides. This nested arrangement maximizes the gate's control over the conduction channel while minimizing the lateral space required, achieving superior leakage control in a compact area.
2Reliability
If FinFETs with gate on multiple sides of channel are used, then conduction and leakage control is improved, but manufacturing process complexity increases
Solution Approach 1:
The fabrication process is divided into distinct sequential stages: forming the fin structure, depositing the gate material, creating source/drain regions, and forming isolation structures. Each stage is independently optimized and controlled, allowing complex FinFET structures to be manufactured through modular, repeatable process steps.
Solution Approach 2:
The fin structure is formed preliminary before gate deposition, establishing the vertical channel architecture in advance. This preliminary formation allows subsequent gate and source/drain processing to be performed on a pre-defined geometry, simplifying the overall manufacturing sequence while ensuring precise conduction control.
3Quantity of substance
If larger number of memory cells are integrated on chip, then chip capacity increases, but transistor resistance and capacitance increase
Solution Approach 1:
By stacking FinFETs vertically, the patent reduces the lateral area required per transistor, enabling higher cell density without increasing interconnect lengths. The vertical configuration shortens the distance between source and drain regions while maintaining effective gate control, thereby reducing both resistance and capacitance despite increased integration density.
Data Source
AI summary
A method of forming a SRAM semiconductor device with reduced area layout and a resulting device are provided. Embodiments include forming a first field effect transistor (FET) over a substrate; forming an insulating material over the first FET; forming a second FET over the insulating material; and patterning the first FET, insulating material and second FET to form fins over the substrate.