Stacked Fin MOS Device With Segmented Gate Regions
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Solution Overview
Problem
The existing three-dimensional stacked fin-CMOS devices face challenges in optimizing the performance, particularly in achieving an optimal ratio of on-state and off-state currents due to the shared gate electrode across both n-type and p-type MOS devices, limiting the ability to independently optimize each device's performance.
Innovation Solution
The MOS device incorporates a protrusion with multiple semiconductor regions separated by isolation regions, featuring a gate electrode with distinct gate regions, each influencing the conduction channel of a separate semiconductor region, allowing for improved performance optimization by varying the work function of the gate materials and using a hard mask region to control the conduction channel's presence on the top surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a shared gate electrode is used for both NMOS and PMOS devices in a stacked fin structure, then device integration is achieved, but independent optimization of on-state and off-state current ratios becomes difficult
Solution Approach 1:
The single gate electrode is divided into multiple gate regions (first gate region and second gate region), each extending over different semiconductor regions (first and second semiconductor regions). This segmentation allows independent control and optimization of NMOS and PMOS device characteristics while maintaining the stacked fin integration structure.
Solution Approach 2:
Different gate regions are assigned different work function values through the use of different gate materials. The first gate region has a first work function value optimized for NMOS operation, while the second gate region has a second work function value optimized for PMOS operation, enabling local optimization of each device type's electrical characteristics.
2Power
If conduction channel is allowed on top surface of stacked semiconductor regions, then current carrying capability is increased, but differences between NMOS and PMOS performance are exacerbated
Solution Approach 1:
The patent selectively positions gate regions to control where conduction channels form. By extending gate regions over specific semiconductor regions and using appropriate work function values, the conduction channel location is controlled to be primarily on sidewalls rather than top surfaces, achieving balanced NMOS and PMOS performance while maintaining adequate current carrying capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the performance of the MOS device by allowing for independent optimization of the on-state and off-state current ratios and improves the current carrying capability of the PMOS device by ensuring the conduction channel is primarily on the sidewalls, thereby minimizing differences between NMOS and PMOS devices.
Implementation Method 1
Each gate region influences the conduction channel of a separate semiconductor region
Implementation Method 2
at least one of the gate regions has a work function with a value different from the work function value of the other gate regions
Data Source
AI summary
The invention provides a three-dimensional stacked fin metal oxide semiconductor (SF-MOS) device (10,30) comprising a protrusion or fin structure with a plurality of stacked semiconductor regions (3,5,12), in which a second semiconductor region (5,12) is separated from a first semiconductor region (3,5) by an isolation region (4,11). A gate isolation layer (8) extends at least over the sidewalls of the protrusion (7) and a gate electrode extends over the gate isolation layer (8). The gate electrode comprises a plurality of gate regions (13,14,15) wherein each gate region (13,14,15) extends over another semiconductor region (3,5,12). In this way each gate region (13,14,15) influences the conduction channel of another semiconductor region (3,5,12) and hence adds another degree of freedom with which the performance of the SF-MOS device (10,30) can be optimized. The invention further provides a method of manufacturing the SF-MOS device (10,30) according to the invention.