Stacked Fin Semiconductor Structure for Uniform Fin Profiles
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Solution Overview
Problem
Existing FinFET devices face challenges in process development due to variations in fin width and profile, particularly at the end of the fin, which affect the complexity and efficiency of semiconductor processing and manufacturing.
Innovation Solution
A method for manufacturing a semiconductor structure that includes a fin structure, where the fin structure is formed by stacking a first conductive type semiconductive layer over a substrate, a dielectric layer between the layers, and a second conductive type semiconductive layer on top, with precise patterning and etching processes to achieve desired fin profiles and densities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fin width and profile are controlled in existing FinFET processes, then device performance is maintained, but manufacturing complexity increases due to variations especially at fin ends
Solution Approach 1:
The fin structure is segmented into multiple conductive type layers (first conductive type and second conductive type) stacked vertically. This segmentation allows independent control of each layer's properties, enabling precise fin width and profile control while simplifying the overall manufacturing process by addressing variations in discrete layers rather than as a monolithic structure.
Solution Approach 2:
Different conductive type layers are assigned to different vertical regions of the fin structure based on local requirements. The first conductive type layer addresses specific regions needing one type of electrical property, while the second conductive type layer addresses other regions needing different properties, optimizing fin width and profile uniformity locally throughout the structure.
2Productivity
If area scaling is pursued to increase functional density, then production efficiency improves, but short-channel effects increase
Solution Approach 1:
The invention transitions from planar area scaling to vertical dimension exploitation by stacking multiple conductive type layers in the vertical direction. This allows functional density to increase through the third dimension rather than compressing features in the planar direction, thereby maintaining larger effective channel dimensions that reduce short-channel effects while achieving higher productivity.
Solution Approach 2:
The fin structure employs composite material architecture with alternating conductive type layers (n-type and p-type semiconductive layers) separated by dielectric layers. This composite structure enables independent optimization of electrical properties in each layer, allowing area scaling for productivity while the multi-layer composition provides electrical isolation and control mechanisms that mitigate short-channel effects.
Data Source
AI summary
A semiconductor structure includes: a substrate and a fin protruding from the substrate. The fin comprises a first semiconductive layer over the substrate, a second semiconductive layer over the first semiconductive layer, and a dielectric layer disposed between the first semiconductive layer and the second semiconductive layer and electrically isolated from the first semiconductive layer and the second semiconductive layer. The semiconductor structure further includes a gate electrode including: a first conductive portion extending along two opposite sidewalls of the first semiconductive layer and along an upper surface of the substrate; and a second conductive portion electrically isolated from the first conductive portion and extending along two opposite sidewalls of the second semiconductive layer and along an upper surface of the fin.