Stacked Fin Transistor Separate Gate Work Function Control
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Solution Overview
Problem
In stacked field effect transistors (FETs), using a common work function metal for both negative channel FET (NFET) and positive channel FET (PFET) is not suitable for voltage threshold balancing and separate gate control, as it restricts independent control of each FET's gate.
Innovation Solution
A method is developed to form separate gates with different work function metals for the upper and lower FETs in a stacked FET configuration, allowing for distinct voltage thresholds by using a sacrificial high silicon germanium layer for dielectric isolation and forming separate gate contacts for each FET.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a common work function metal is used for both NFET and PFET in stacked FETs, then the manufacturing process is simplified, but independent gate control and voltage threshold balancing are compromised
Solution Approach 1:
The patent divides the previously unified gate structure into separate upper and lower gates. The upper gate is formed over the NFET channel and the lower gate is formed over the PFET channel, allowing independent work function metal selection and voltage control for each transistor type while maintaining the stacked vertical architecture
Solution Approach 2:
The patent applies different work function metals locally to different regions: a first work function metal (e.g., titanium nitride) is applied to the upper gate for NFET, while a second work function metal (e.g., tungsten) is applied to the lower gate for PFET. This local differentiation enables precise threshold voltage control for each transistor type
2Manufacturing precision
If separate gates with different work function metals are used for upper and lower FETs, then voltage threshold balancing and independent gate control are achieved, but device structure and manufacturing complexity increase
Solution Approach 1:
The patent transitions from a planar gate structure to a vertical stacked gate structure. The upper and lower gates are arranged vertically along the fin height, with the upper gate positioned above the NFET channel and the lower gate positioned below the PFET channel, enabling separate control while maintaining a compact footprint
Solution Approach 2:
The patent forms a sacrificial dielectric layer (e.g., silicon oxide) between the upper and lower gates during the formation process. This preliminary dielectric layer is later removed to create the separated gate structure, ensuring proper isolation and preventing electrical interference between the two gates during manufacturing
Data Source
AI summary
Forming a first opening in a first double stacked fin and forming a second opening in a second double stacked fin, by removing a high silicon germanium layer, forming a low k spacer, removing a dummy gate, and removing portions of the low k spacer from an outer surface of the first double stacked fin, and an outer surface of the second double stacked fin. A structure including an upper fin of a double stacked fin separated from a lower fin of a double stacked fin by a low k spacer and by a p type field effect transistor work function metal layer (PFET WFM), where a horizontal lower surface of the upper fin is coplanar with a horizontal upper surface of the low k spacer and a horizontal lower surface of the low k spacer is coplanar with a horizontal upper surface of the PFET WFM.