Stacked FinFET Source/Drain Epitaxy for Short-Channel Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices become more integrated and smaller in size, they face challenges in maintaining high performance and electrical characteristics due to reduced dimensions, particularly in planar metal oxide semiconductor FETs, which can lead to limitations in operating characteristics and increased complexity in manufacturing.
Innovation Solution
A semiconductor device design featuring a substrate with active regions, multiple semiconductor layers, and a gate structure that surrounds these layers, including epitaxial source/drain regions with specific layer compositions and structures to enhance electrical performance and suppress short-channel effects, while also improving the growth and distribution of epitaxial layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration of semiconductor devices is increased to meet demand for high performance and high speed, then the functionality and operating speed are improved, but the patterns have fine widths or fine spacings which causes limitations in operating characteristics
Solution Approach 1:
The patent transitions from planar metal oxide semiconductor FET to FinFET with three-dimensional channel structure. The active region is formed as a fin extending vertically from the substrate, and the gate structure wraps around the fin in a multi-dimensional configuration, enabling improved electrical characteristics while maintaining small footprint for high integration density
Solution Approach 2:
The channel region is divided into multiple segments along the vertical direction with different semiconductor layers (first semiconductor layer, second semiconductor layer, third semiconductor layer) having different materials or doping concentrations. This segmentation allows optimization of carrier transport in different regions, improving mobility and reducing short-channel effects while maintaining fine pattern dimensions
2Volume of moving object
If the size of planar metal oxide semiconductor FET is reduced to increase integration, then the integration density is improved, but the operating characteristics are limited due to reduced dimensions
Solution Approach 1:
The invention reduces the planar footprint by forming a three-dimensional FinFET structure where the channel extends vertically. The gate structure surrounds the fin channel in multiple directions, achieving high integration density with small device area while maintaining excellent electrical characteristics through the vertical channel configuration
Solution Approach 2:
The patent employs composite material structure with different semiconductor layers (e.g., SiGe, Si, GaAs) stacked vertically in the channel region. Each layer is optimized for specific functions such as high mobility transport or stress engineering, enabling superior operating characteristics in a compact device footprint
3Reliability
If epitaxial layers are grown to form source/drain regions in FinFET structure, then the electrical characteristics are improved, but the growth uniformity and impurity distribution control become more difficult
Solution Approach 1:
The source/drain epitaxial growth is performed with locally optimized conditions for different regions. The first epitaxial layer is grown with specific doping concentration in the lower source/drain region, while the second epitaxial layer is grown with different doping concentration in the upper source/drain region. This local quality control ensures uniform growth and precise impurity distribution tailored to each region's electrical requirements
Solution Approach 2:
The patent performs preliminary epitaxial growth of source/drain layers before final gate formation. The first and second epitaxial layers are grown with controlled doping profiles in advance, establishing the electrical characteristics of source/drain regions before subsequent processing steps. This preliminary action ensures uniform growth and precise impurity distribution is achieved before the structure becomes more complex
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed semiconductor device design improves electrical characteristics by optimizing the epitaxial layer growth and impurity distribution, reducing short-channel effects, and enhancing the overall performance and integration density of semiconductor devices.
Implementation Method 1
the source/drain region includes first epitaxial layers and a second epitaxial layer
Data Source
AI summary
A semiconductor device includes: an active region on a substrate extending in a first direction; a plurality of semiconductor layers spaced apart from each in a vertical direction on the active region, the plurality of semiconductor layers including lower and upper semiconductor layers; a gate structure on the substrate extending in a second direction to intersect the active region and the plurality of semiconductor layers; and a source/drain region on the active region and contacting the plurality of semiconductor layers. The source/drain region includes first epitaxial layers, including first layers on a side surface of the lower semiconductor layer and a second layer provided on and contacting the active region, and a second epitaxial layer contacts a side surface of the upper semiconductor layer in the first direction, and the first layer is between the second epitaxial layer and the side surface of the lower semiconductor layer.