Stacked FinFET Over GAA Transistors for Voltage-Compatible Embedded Memory
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Solution Overview
Problem
The incompatibility of voltage requirements between advanced logic technology using GAA transistors and embedded DRAM necessitates a solution for integrating high-performance compute logic and high-density memory on a single die, as GAA transistors are not suitable for providing high-voltage transistors needed for embedded DRAM.
Innovation Solution
Integrating FinFETs over GAA transistors in a stacked complimentary FET architecture, where FinFETs provide high-voltage transistors suitable for peripheral logic and GAA transistors provide compute logic, enabling embedded 1T-1X based memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If GAA transistors are used for advanced logic technology, then compute logic performance is improved, but voltage compatibility for embedded DRAM is lost
Solution Approach 1:
The patent segments the transistor requirements by creating two distinct layers: a first layer with GAA transistors for high-performance compute logic, and a second layer with FinFETs for high-voltage embedded DRAM. This segmentation allows each layer to be optimized for its specific function without compromise.
Solution Approach 2:
The patent transitions from a planar integration approach to a vertical stacked architecture, placing FinFETs over GAA transistors in different layers. This dimensional change enables both transistor types to coexist on a single die while maintaining their respective voltage requirements and performance characteristics.
2Quantity of substance
If transistor size is scaled down, then functional unit density is increased, but voltage requirements become incompatible
Solution Approach 1:
The patent segments the die into functional layers: advanced logic units with scaled GAA transistors in the first layer, and embedded DRAM with FinFETs in the second layer. This allows high-density integration of scaled transistors while maintaining voltage compatibility for memory operations.
Solution Approach 2:
Different regions and layers of the die have different transistor types optimized for their specific functions: GAA transistors in the first layer provide high-performance logic with scaled dimensions, while FinFETs in the second layer provide high-voltage capability for embedded DRAM.
3Adaptability or versatility
If FinFETs are integrated over GAA transistors, then voltage incompatibility is resolved, but device structure becomes more complex
Solution Approach 1:
The patent resolves voltage incompatibility by moving to a vertical stacked architecture where FinFETs are integrated over GAA transistors in different layers. This three-dimensional integration enables both voltage requirements to be satisfied while maintaining a compact footprint.
Solution Approach 2:
The patent implements a nested structure where the second layer containing FinFETs is positioned over the first layer containing GAA transistors. This nesting approach allows both transistor types to be integrated in a compact vertical arrangement, managing complexity through hierarchical organization.
Data Source
AI summary
Described herein are integrated circuit (IC) devices that include devices that include fin-based field-effect transistors (FinFETs) integrated over gate-all-around (GAA) transistors. The GAA transistors may serve to provide high-performance compute logic, and may be relatively low-voltage transistors, while FinFETs may be more suitable than GAA transistors for providing high-voltage transistors, and, therefore, may serve to provide peripheral logic for backend memory arrays implemented over the same support structure over which the GAA transistors and the FinFETs are provided. Such an arrangement may address the fundamental voltage incompatibility by integrating a mix of FinFETs and GAA transistors in stacked complimentary FET (CFET) architecture to enable embedded 1T-1X based memories.