Stacked FinFET Mask-Programmable ROM With Segmented Thresholds
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Solution Overview
Problem
Existing methods for co-integrating non-volatile memories with stacked FinFET structures are complex and require simplified processing steps to enable efficient implementation in stacked FinFET circuits.
Innovation Solution
A stacked FinFET mask-programmable ROM is developed, featuring a fin structure with programmable semiconductor fin portions and insulator fin portions, allowing for programming during manufacturing and enabling efficient memory integration through a simpler process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If existing methods are used to co-integrate non-volatile memories with stacked FinFET, then memory integration is achieved, but the processing steps become complex
Solution Approach 1:
The fin structure is divided into multiple programmable semiconductor fin portions (first, second, third portions) with different threshold voltages, allowing independent programming of each portion. This segmentation enables complex memory functionality to be achieved through simpler, modular processing steps rather than requiring complex integrated processing.
Solution Approach 2:
Different regions of the fin structure are assigned different threshold voltage characteristics (first threshold voltage for first portion, second for second portion, third for third portion). This local differentiation allows each region to be programmed independently with appropriate characteristics, simplifying the overall integration process while maintaining functional complexity.
2Adaptability or versatility
If multiple programmable fin portions with different threshold voltages are integrated, then memory functionality is enhanced, but structural complexity increases
Solution Approach 1:
The semiconductor fin is segmented into multiple programmable portions, each capable of storing different data values through different threshold voltages. This segmentation provides enhanced memory functionality by allowing multiple bits to be stored in a single vertical structure, improving adaptability without requiring proportional increases in lateral device count.
Solution Approach 2:
The invention transitions from traditional lateral memory cell arrangements to a vertical stacking architecture where multiple programmable fin portions are stacked vertically. This dimensional change from 2D to 3D integration enhances memory functionality and density while managing structural complexity through vertical rather than lateral expansion.
3Quantity of substance
If stacked FinFET structures are used, then density scaling is achieved, but integration with non-volatile memory becomes complex
Solution Approach 1:
The invention merges the stacked FinFET transistor structure with non-volatile memory cells in a unified integrated architecture. The same vertical fin structure serves both as the transistor channel and as the memory storage element, eliminating the need for separate memory cell structures and simplifying the integration process while maintaining high density.
Solution Approach 2:
The stacked fin structure is designed to serve multiple functions: it acts as the transistor channel for switching operations and simultaneously serves as the memory storage element through its programmable threshold voltage portions. This multi-functionality reduces integration complexity by eliminating the need for dedicated separate memory structures.
Data Source
AI summary
A stacked FinFET mask-programmable read only memory (ROM) is provided. The stacked FinFET mask-programmable ROM includes a fin structure extending upward from an insulator layer. In accordance with the present application, the fin structure includes, from bottom to top, a lower programmable semiconductor fin portion having a first threshold voltage, an insulator fin portion, and an upper programmable semiconductor fin portion having a second threshold voltage. A lower gate structure contacts a sidewall of the lower programmable semiconductor fin portion, and an upper gate structure contacts a sidewall of the upper programmable semiconductor fin portion.