Stacked FinFET Transistors for Scaling Device Density
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Solution Overview
Problem
Integrated circuit devices face challenges in scaling to smaller sizes without degrading the minimum voltage at which they can reliably operate, leading to performance variations.
Innovation Solution
The solution involves stacking transistors on a semiconductor substrate with fin structures, including isolation layers and channel layers, where gate terminals are capacitively coupled to control electrical current flow, and contacts are strategically positioned to manage current between channel layers, allowing for efficient scaling without performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor sizing and spacing are reduced to enable scaling, then device density increases, but performance parameter variation increases and minimum operating voltage degrades
Solution Approach 1:
The patent transitions from planar transistor scaling to three-dimensional FinFET structures with vertical channel extensions. By growing fins perpendicular to the substrate and stacking multiple channel layers vertically, the design exploits the third dimension to increase effective channel area and device density without further reducing lateral dimensions, thereby avoiding the performance degradation associated with continued planar scaling
Solution Approach 2:
The patent implements stacked FinFET structures where multiple channel layers are vertically nested one above another, sharing common source and drain regions. This nesting approach allows multiple transistor channels to be packed within a compact vertical space, increasing device density while maintaining controlled electrical characteristics through shared contact regions
2Area of moving object
If transistor dimensions are reduced for scaling, then area decreases, but manufacturing precision requirements increase due to variation in performance parameters
Solution Approach 1:
The patent divides the transistor channel into multiple discrete FinFET segments stacked vertically, each with its own gate control. This segmentation allows independent optimization and control of each channel layer's electrical characteristics, reducing the impact of variations in any single layer and improving overall manufacturing precision
Solution Approach 2:
The patent modifies the channel geometry from two-dimensional planar to three-dimensional vertical fins, changing the critical dimensional parameters from lateral gate length to vertical fin height and width. This parameter transformation enables scaling while maintaining better control over effective channel area and reducing sensitivity to lateral dimension variations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the scaling of integrated circuit devices to smaller dimensions while maintaining reliable operation and performance, specifically by ensuring consistent minimum voltage levels.
Implementation Method 1
gate terminals capacitively coupled to control electrical current flow
Data Source
AI summary
Embodiments of the present disclosure provide techniques and configurations for stacking transistors of a memory device. In one embodiment, an apparatus includes a semiconductor substrate, a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes a first isolation layer disposed on the semiconductor substrate, a first channel layer disposed on the first isolation layer, a second isolation layer disposed on the first channel layer, and a second channel layer disposed on the second isolation layer, and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for a first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for a second transistor. Other embodiments may be described and/or claimed.