Stacked NOR Flash Decoder Layout for Smaller Planar Area
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Solution Overview
Problem
Conventional NOR-type flash memory chips occupy a large planar area, failing to meet the demand for smaller volumes in modern applications.
Innovation Solution
A semiconductor device is designed with a first chip containing a memory array and a second chip vertically stacked on the first, where local word and bit line decoders are integrated within the top-down projection region of the array block on the second chip, connected via a bonding structure, reducing the planar area and maintaining orderly wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a memory array with word line decoder and bit line decoder is arranged in a conventional planar layout, then the decoders can control the memory cells, but the overall planar area occupied is large
Solution Approach 1:
The patent transitions from a conventional planar layout to a three-dimensional stacked architecture. The memory array is formed on a first substrate while the word line decoder and bit line decoder are integrated on a second substrate stacked vertically above the first substrate. This vertical stacking enables the decoders to control memory cells without occupying additional planar area, effectively resolving the contradiction between decoder functionality and planar area consumption.
2Ease of manufacture
If decoders are placed at the periphery of the memory array, then wiring layout can be organized, but the overall chip volume increases
Solution Approach 1:
Instead of expanding the chip volume horizontally by placing decoders at the periphery, the patent moves the decoders to a vertical dimension by stacking them on a separate substrate above the memory array. This approach maintains organized wiring through vertical interconnects while preventing horizontal expansion, thus resolving the contradiction between manufacturability and chip volume.
Solution Approach 2:
The patent divides the chip into functionally independent modules: the memory array on the first substrate and the decoders on the second substrate. This segmentation allows each module to be optimized independently and connected through vertical interconnects, reducing the overall chip volume while maintaining organized wiring relationships.
3Area of stationary object
If local word line decoder and local bit line decoder are stacked vertically on the first chip, then planar area is reduced, but electrical connection complexity increases
Solution Approach 1:
The patent resolves the connection complexity issue by establishing systematic vertical electrical connections between the stacked substrates. Conductive structures are formed to connect the memory cells on the first substrate with the decoders on the second substrate, enabling signal transmission in the vertical dimension. This approach reduces planar area while managing electrical connection complexity through structured vertical interconnects rather than chaotic routing.
Data Source
AI summary
The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes stacked first and second chips, a local word line decoder and a local bit line decoder for controlling an array block are disposed in the second chip, and the first chip forms an electrical connection with the second chip. At least one of the local word line decoder block and the local bit line decoder block formed by the local word line decoder block and the local bit line decoder block respectively is arranged within the top-down projection region of the array block in the second chip.