Stacked Integrated Circuit Assembly via Vertical Flip-Chip Interconnects
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Solution Overview
Problem
It is not always feasible to integrate all electronic components into a single integrated circuit due to compatibility issues between production processes or economic constraints, leading to the need for using multiple integrated circuits in certain applications where space or high-frequency performance is critical.
Innovation Solution
A stacked integrated circuit assembly is proposed, comprising a substrate with connection pads, a first flip chip integrated circuit (FFIC) and a second flip chip integrated circuit (SFIC) stacked on top of each other, connected via solder connections and through die vias, allowing for efficient processing of microwave frequency signals while minimizing footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all electronic components are integrated into a single integrated circuit, then electrical performance is improved and space is reduced, but production process compatibility and economic feasibility deteriorate
Solution Approach 1:
The patent divides the electronic system into multiple separate integrated circuits (analog IC, digital IC, RF IC) that can be manufactured using different production processes optimized for each type. These segmented ICs are then stacked vertically to achieve integration benefits without requiring all components to be fabricated in a single IC using a single production process.
Solution Approach 2:
The patent transitions from a planar arrangement of electronic components to a three-dimensional stacked configuration. By stacking multiple ICs vertically on top of each other with interconnect structures, the system achieves high-density integration and improved electrical performance without the need for all components to coexist on a single IC substrate.
2Area of stationary object
If all electronic components are integrated into a single integrated circuit, then footprint is reduced, but production cost and complexity increase
Solution Approach 1:
The system is segmented into multiple specialized ICs (analog, digital, RF) that can be designed and manufactured independently with optimized processes for each type, reducing the complexity of integrating all functions into a single IC while achieving compact footprint through vertical stacking.
Solution Approach 2:
Multiple ICs are nested vertically in a stacked configuration, with each IC containing specific functional components. This nesting approach achieves high-density integration and minimal footprint while allowing each IC to be manufactured with appropriate process complexity for its specific function.
3Reliability
If electronic components are placed closer together, then electrical performance is improved, but parasitic effects increase
Solution Approach 1:
The patent places electronic components in close proximity by stacking ICs vertically in the third dimension, rather than placing them close together in the same plane. This vertical arrangement achieves short signal paths and improved electrical performance while the layered structure helps manage parasitic effects through controlled interconnect design between layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stacked assembly provides improved electrical performance and reduced footprint, enabling efficient processing of high-frequency signals and mitigating performance degradation associated with separate integrated circuits, while maintaining economic viability.
Implementation Method 1
The stacked integrated circuit assembly includes at least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC
Data Source
AI summary
In one or more embodiments, a method of producing a stacked integrated circuit assembly includes providing a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC may be disposed between the substrate and the SFIC. The method includes making at least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.