Stacked Flip-Chip Power Module for Compact Thermal Management

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Solution Overview

Problem

Conventional stack type power modules are limited in size reduction due to wire bonding, which also affects their operational characteristics and complexity in sealing processes.

Innovation Solution

A power module with a stacked flip-chip configuration, using a lead frame, interconnecting substrate, and thermal substrate, where power and control device chips are attached via flip-chip bonding, eliminating the need for wire bonding and allowing for a compact design with improved thermal management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If wire bonding is used to connect chips to lead frame, then electrical connection is achieved, but the size of the power module increases and operational characteristics deteriorate

Engineering Contradiction:
Improvesize of power moduleVSAvoidoperational characteristics
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent inverts the conventional connection approach by using flip-chip technology where chips are mounted face-down directly on the lead frame, eliminating the need for wire bonding. This inversion of the mounting method reduces module size while improving operational characteristics through shorter current paths and reduced inductance.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent extracts and eliminates the wire bonding process from the power module structure. By removing the wires and adopting direct chip-to-lead-frame connection through flip-chip mounting, the module size is reduced and reliability is improved through fewer potential failure points.

Inventive Principle:
Principle #2Taking out (Extraction)

2Ease of manufacture

If wire bonding is used to connect chips, then electrical connection is established, but the sealing process becomes more complex

Engineering Contradiction:
Improvesealing process complexityVSAvoidwire bonding structure
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent removes the wire bonding structure from the device, eliminating the need for complex sealing around wires. The flip-chip mounting method allows for simpler sealing processes as there are no protruding wires requiring protection.

Inventive Principle:
Principle #2Taking out (Extraction)

3Temperature

If chips are mounted using conventional methods, then assembly is achieved, but thermal management efficiency is reduced due to thermal conductivity mismatch

Engineering Contradiction:
Improvethermal management efficiencyVSAvoidthermal conductivity mismatch
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent changes the mounting parameters by using flip-chip technology with direct contact between chip pads and lead frame, improving thermal conductivity. This parameter change in the connection method eliminates thermal resistance interfaces and reduces thermal conductivity mismatch, enhancing heat dissipation efficiency.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9130065B2Power module having stacked flip-chip and method for fabricating the power module
Publication Date: 2015.09.08 SEMICON COMPONENTS IND LLC
  • US9130065B2 patent drawing
  • US9130065B2 patent drawing
  • US9130065B2 patent drawing

AI summary

Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method. The method includes forming bumps on power and control device chips on a wafer level; separately sawing the power and control device chips into individual chips; adhering the power device chip onto a thermal substrate and the control device chip onto an interconnecting substrate; combining a lead frame, the thermal substrate, and the interconnecting substrate with one another in a multi-jig; and sealing the power and control device chips, and the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.