Stacked Floating Gate Interference Reduction via Insulator Mediator
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Solution Overview
Problem
Three-dimensional non-volatile memory devices with stacked floating gates face interference issues that deteriorate their characteristics, limiting their performance and integration capabilities.
Innovation Solution
A semiconductor device design featuring a channel layer with protrusions extending from its sidewall, surrounded by floating gates with a level difference between their lateral surfaces, and control gates stacked along the channel layer, along with interlayer insulating layers to reduce interference between the floating gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional non-volatile memory devices with stacked floating gates are implemented to increase integration density, then the degree of integration is improved, but interference between stacked floating gates increases and deteriorates device characteristics
Solution Approach 1:
An interlayer insulating layer is introduced as an intermediary between stacked floating gates to reduce capacitive coupling and interference effects. This mediator layer allows the floating gates to be closely stacked for high integration while maintaining electrical isolation, thus resolving the contradiction between integration density and interference reduction.
Solution Approach 2:
The floating gates are designed to maintain consistent potential across their surfaces through careful structural design and material selection. By ensuring equipotential conditions, the interference between adjacent floating gates is minimized, allowing for dense stacking without significant performance degradation.
2Quantity of substance
If floating gates are stacked closely to increase memory cell density, then the quantity of memory cells is improved, but coupling effects between floating gates increase and deteriorate device characteristics
Solution Approach 1:
The interlayer insulating layer serves as a mediator that enables close stacking of floating gates for high memory cell density while simultaneously reducing unwanted coupling effects. This intermediary layer provides the necessary electrical isolation to prevent harmful interactions between adjacent floating gates.
Solution Approach 2:
The dielectric properties of the interlayer insulating layer are carefully selected and optimized to change the electrical parameters between floating gates. By adjusting the permittivity and thickness of this layer, the coupling effects are controlled to maintain low interference while enabling dense stacking for high memory cell density.
Data Source
AI summary
A semiconductor device includes a channel layer protruding from a substrate and having protrusions extending from a sidewall thereof. Floating gates surrounding the channel layer are provided between the protrusions. Control gates surrounding the floating gates are stacked along the channel layer. Interlayer insulating layers are interposed between the control gates stacked along the channel layer. A level difference exists between a lateral surface of each of the floating gates, and a lateral surface of each of the protrusions.