Stacked Forksheet Transistor Gate Contacts for MOL Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor technologies lack a viable embedded contact scheme for stacked forksheet transistors at the MOL level, which is necessary for achieving optimal circuit density and performance in 2 nm nodes and beyond.
Innovation Solution
The semiconductor structure includes a pair of stacked forksheet transistors separated by a dielectric wall structure, with shared or non-shared top gate electrodes, and a frontside or backside contact scheme that allows for independent or merged gate contacts, enabling efficient electrical connections and improved circuit density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a stacked forksheet transistor structure is implemented, then circuit density and performance are improved, but device complexity increases due to the need for separate gate contacts at the MOL level
Solution Approach 1:
The patent merges the gate contact structures by forming a common contact region that provides electrical connection to both the first and second gate electrodes through a shared conductive path. This merging approach eliminates the need for separate embedded contacts at the MOL level, thereby reducing device complexity while maintaining the high circuit density enabled by the stacked forksheet configuration.
Solution Approach 2:
The common contact region serves multiple functions simultaneously: it provides electrical connection to both gate electrodes, acts as an isolation structure between the stacked transistors, and enables the stacked configuration itself. This multi-functionality reduces the number of discrete components needed and simplifies the overall device architecture.
2Reliability
If separate embedded contact structures are used for each gate, then electrical connection is ensured, but manufacturing precision requirements increase
Solution Approach 1:
By combining the contact structures into a single common contact region, the patent eliminates the need for precise alignment between multiple separate contacts. The unified structure ensures electrical connection to both gates while significantly reducing manufacturing precision requirements, as only a single contact region needs to be formed and aligned.
3Productivity
If tighter n-to-p spacing is achieved through dielectric wall structure, then performance improves, but device complexity increases
Solution Approach 1:
The dielectric wall structure serves dual purposes: it provides electrical isolation between the n-type and p-type forksheet transistors enabling tighter spacing, and it serves as the substrate upon which the common contact region is formed. This multi-functionality allows performance improvement through tighter spacing without proportionally increasing device complexity.
Data Source
AI summary
Semiconductor structures including stacked transistors are provided. The semiconductor structures can include a pair of stacked forksheet transistors that have a shared second (top) gate electrode, or the structures can include a pair of stacked forksheet transistors that have non-shared second (top) gate electrodes. In either of these embodiments, the second (top) gate electrode is separated from a first (bottom) gate electrode by a frontside gate cut structure.