Stacked Forksheet Transistors With Isolation Walls for Short-Circuit Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving higher device density and performance while minimizing miniaturization, particularly in nanosheet transistors, due to issues with short-circuit risks and limited area gains in forksheet transistor structures.
Innovation Solution
A 3D-stacked semiconductor device with forksheet transistors is designed, featuring an isolation wall that electrically isolates parallel nanosheet transistors and includes active contacts that contact the isolation wall, reducing short-circuit risks and enabling additional area gains through optimized layout and manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If nanosheet transistors are stacked vertically to increase device density, then device density and current control improve, but short-circuit risks increase between adjacent nanosheet channels
Solution Approach 1:
The patent divides the continuous nanosheet channel structure into separate segments by introducing recesses that penetrate through the channel stack. These recesses create isolated channel regions (first channel structure and second channel structure) that are electrically separated, preventing short-circuits while maintaining high device density through vertical stacking.
Solution Approach 2:
The patent introduces an intermediate structure (recess or isolation region) between adjacent nanosheet channels to prevent direct electrical contact. This intermediate element acts as a mediator that maintains the necessary electrical isolation between channels while allowing the overall stacked structure to achieve high density.
2Volume of moving object
If forksheet transistor structure is used to achieve miniaturization, then device size reduces, but manufacturing complexity increases due to additional isolation structures
Solution Approach 1:
The patent combines multiple functions into the recess structure: it serves as both the isolation element separating adjacent channels and as part of the active device structure itself. The recess is formed through the channel stack to create both the separation and define the active channel regions, reducing the need for additional separate isolation structures and simplifying manufacturing.
Solution Approach 2:
The patent transitions from planar isolation approaches to vertical dimension isolation by forming recesses that penetrate through the thickness of the channel stack. This dimensional change allows isolation to be achieved in the vertical direction rather than requiring complex lateral isolation structures, thereby reducing device footprint and manufacturing complexity.
3Reliability
If isolation wall is added to separate nanosheet transistors, then short-circuit risk reduces, but device area increases
Solution Approach 1:
The patent moves the isolation function from the lateral plane to the vertical dimension by forming recesses that penetrate through the channel stack thickness. This allows electrical isolation to be achieved without adding lateral area, as the separation is accomplished through depth rather than width, maintaining compact device footprint while preventing short-circuits.
Solution Approach 2:
The isolation structure (recess) is nested within the channel stack itself rather than being added as an external element. The recess is formed by removing material from the existing channel structure, creating isolation regions that are integrated into the stack volume, thereby avoiding additional area consumption while achieving effective electrical separation.
Data Source
Figure 1A
Figure 1B~1C
Figure 2
AI summary
Provided is a semiconductor device comprising a 1st source/drain pattern; a 1st active contact on the 1st source/drain pattern; and an isolation wall contacting the 1st active contact. Provided is also semiconductor device which includes: a 1st source/drain pattern; a 2nd source/drain pattern; an isolation wall between the 1st source/drain pattern and the 2nd source/drain pattern; a 1st active contact on the 1st source/drain pattern; and a 2nd active contact on the 2nd source/drain pattern, wherein the 1st active contact contacts a 1st side surface of the isolation wall, and the 2nd active contact contacts a 2nd side surface of the isolation wall, opposite to the 1st sidewall.