Stacked FPGA Software Model Interchip Interface
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Solution Overview
Problem
The operation of field programmable gate array (FPGA) systems is limited by I/O resources, including speed and power consumption, which restricts the utilization of additional integrated circuit (IC) resources when stacked with an FPGA, necessitating improved modeling techniques for characterization and resource utilization.
Innovation Solution
A software model of a stacked FPGA system is developed, featuring an interchip communication interface that connects an FPGA die to a second IC die through a configurable internal interface, allowing high-speed characterization and resource integration, with thousands of micro-bump interconnects providing high bandwidth and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional I/O resources are used to connect stacked IC to FPGA, then device integration is achieved, but speed and power consumption are limited
Solution Approach 1:
The patent introduces an interchip communication interface as an intermediary component between the FPGA die and stacked IC die. This interface includes configuration logic and routing resources that directly mediate communication between the two dies, eliminating the need for external I/O blocks and achieving high-speed connection with reduced power consumption.
Solution Approach 2:
The patent transitions from traditional two-dimensional I/O-based interconnection to three-dimensional direct interchip communication through stacked die architecture. The interchip communication interface enables vertical communication paths through the stack, providing high-bandwidth connections that overcome the limitations of planar I/O resources.
2Productivity
If I/O blocks are used for interchip communication, then connectivity is established, but I/O resources are consumed and speed is limited
Solution Approach 1:
The patent extracts the communication function from traditional I/O blocks and creates a dedicated interchip communication interface. This separation allows I/O resources to be freed for other purposes while the extracted communication path provides optimized high-speed connectivity between FPGA and stacked IC resources.
Solution Approach 2:
The interchip communication interface is designed with configurable logic and routing resources that can accommodate multiple communication patterns and protocols. This universal interface can handle various types of data transfer between stacked ICs and FPGA fabric, making it adaptable to different application requirements without consuming dedicated I/O resources.
Data Source
AI summary
A software model (620) of a stacked integrated circuit system (600) includes a first integrated circuit die (602) connected to a second integrated circuit die (604) through an interchip communication interface (606). A software model of the first integrated circuit die includes an integrated circuit resource (614) and an internal interface (150). A software model of the second integrated circuit die includes a stacked resource (618). The software model of the internal interface is configurable to connect the stacked resource of the second integrated circuit die to the integrated circuit resource through the interchip communication interface.