Stacked FPGA Substrates for Signal Delay Reduction
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Solution Overview
Problem
Conventional FPGAs face challenges in reducing minimum feature size due to increased signal delay and parasitics in conductors, which become unacceptable at technology nodes like 45 nanometers, especially for global horizontal and vertical interconnect circuitry.
Innovation Solution
The solution involves separating the circuits of an FPGA into at least two stacked semiconductor substrates, with logic elements on one substrate and non-logic elements on another, reducing the length of global buses and minimizing delays and parasitics, and relocating non-logic elements based on circuit delay analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the minimum feature size is reduced to increase circuit density, then more circuits can be integrated, but signal delay and parasitics in conductors increase to unacceptable levels
Solution Approach 1:
The patent divides the FPGA into multiple separate integrated circuit substrates, each handling specific functions (logic elements, I/O elements, interconnect circuitry). This segmentation reduces the physical distance signals must travel on each substrate, thereby reducing signal delay and parasitics while maintaining high circuit density through increased overall integration.
Solution Approach 2:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture where multiple substrates are vertically arranged and interconnected. This dimensional change allows global interconnect circuitry to be distributed across multiple layers, reducing the length of conductors and associated delays while increasing overall circuit capacity.
2Device complexity
If all circuits are integrated on a single substrate, then device complexity is reduced, but the length of global buses increases causing unacceptable delays
Solution Approach 1:
The patent segments the FPGA into multiple specialized substrates (logic elements substrate, I/O elements substrate, interconnect circuitry substrate). This segmentation places interconnect circuitry on dedicated substrates closer to the logic elements that use it, significantly reducing global bus length and signal delay while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
The patent introduces intermediate substrates that handle specific functions (such as I/O elements or interconnect circuitry) between the logic elements and external connections. These intermediary substrates reduce the distance signals must travel across the entire device, thereby reducing global bus length and delay while keeping each individual substrate relatively simple.
3Reliability
If substrate size is reduced to decrease parasitics, then signal quality improves, but logic element density decreases
Solution Approach 1:
The patent uses a three-dimensional stacked substrate architecture where multiple layers are vertically interconnected. This allows logic elements to be densely packed on each individual substrate while maintaining short interconnect lengths within that substrate. The vertical stacking provides additional routing dimensions, reducing the need for long horizontal conductors and associated parasitics while preserving high logic element density.
Data Source
AI summary
A semiconductor system in a package separates those circuits in a field programmable gate array (FPGA) into two substrates. In particular, the logic elements are formed in a first semiconductor substrate and certain non-logic elements are formed in a second semiconductor substrate that is in mechanical and electrical connection with the first substrate. The two substrates are enclosed in a suitable protective package and electrical connections are provided between one or both substrates and the exterior. The non-logic elements formed in the second substrate are located in circuits that would have a signal propagation delay in a conventional FPGA that is more than approximately twice the interconnect delay between the two substrates.