Vertically Stacked GAA CFET Channels for Density and Vt Tuning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing complementary field effect transistors (C-FET) structures, particularly in sub-10 nanometer technology process nodes, face challenges in device density, performance, and cost due to limitations in fabrication and design.
Innovation Solution
The proposed solution involves a method for forming a complementary FET (CFET) with a first transistor and a second transistor stacked vertically, each with a gate-all-around (GAA) configuration. The method includes forming semiconductor stacks with alternating layers, replacing sacrificial layers, and forming metal gate structures around the semiconductor channel layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional planar FET structures are used, then fabrication is simpler, but device density is limited
Solution Approach 1:
The patent transitions from traditional planar (2D) FET structures to vertically stacked 3D structures, enabling multiple transistors to be stacked in the vertical dimension. This dimensional change increases device density by utilizing the third spatial dimension while maintaining fabrication feasibility through adapted process flows.
Solution Approach 2:
The device is segmented into multiple independent transistor stacks (n-type and p-type) stacked vertically, with each stack containing multiple channel layers. This segmentation allows independent optimization of each transistor type while achieving high overall density through vertical integration.
2Reliability
If same semiconductor material is used for both n-type and p-type devices, then manufacturing is simpler, but device performance is limited
Solution Approach 1:
Different semiconductor materials are used for n-type and p-type transistor channels based on their specific performance requirements. The n-type channels use materials optimized for electron transport while p-type channels use materials optimized for hole transport, achieving local optimization of material properties for each transistor type's specific function.
3Adaptability or versatility
If conventional FET structures are used, then design is simpler, but Vt tuning flexibility is limited
Solution Approach 1:
The patent implements dynamically adjustable threshold voltages through selectable material combinations and configurable stack arrangements. The Vt can be tuned by selecting different semiconductor materials for channels and barriers, allowing adaptive optimization of device characteristics for different operating conditions and application requirements.
Data Source
AI summary
A method includes forming a first stack of alternating first semiconductor layers and first sacrificial layers over a substrate; forming a second stack of alternating second semiconductor layers and second sacrificial layers over the first stack, wherein the first semiconductor layers and the second semiconductor layers are made of different materials; replacing the first sacrificial layers with third sacrificial layers; removing the second sacrificial layers, such that the second semiconductor layers are suspended over the substrate; after removing the second sacrificial layers, removing the third sacrificial layers, such that the first semiconductor layers are suspended over the substrate; forming a first metal gate structure wrapping around the first semiconductor layers; and forming a second metal gate structure wrapping around the second semiconductor layers.