Stacked GAA CFET Structure With Tuned Isolation and Gate Profiles
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Solution Overview
Problem
Existing complementary field effect transistor (C-FET) structures, particularly those with stacked n-type and p-type multi-gate transistors, face challenges in achieving optimal device performance and integration in sub-10 nanometer technology nodes due to fabrication and design issues.
Innovation Solution
A Gate-All-Around (GAA) transistor structure is developed, where transistors are stacked vertically with controlled profiles and dimensions, utilizing multi-step etching processes to form CFETs with overlapping top and bottom transistors, allowing for precise tuning of isolation structures and gate dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional planar FET structures are used, then fabrication processes are simpler, but device density and integration are limited
Solution Approach 1:
The patent transitions from planar (2D) FET structures to vertically stacked 3D structures, enabling multiple transistors to be integrated in the vertical dimension. This dimensional change allows higher device density without increasing lateral footprint, resolving the contradiction between simplicity and density by exploiting the third dimension for integration.
Solution Approach 2:
The patent implements nested transistor structures where n-type and p-type FETs are stacked vertically with shared components and overlapping regions. The transistors are arranged in a nested configuration where gate structures, channel regions, and isolation layers are interlaced in the vertical dimension, enabling high density while managing complexity through systematic nesting patterns.
2Productivity
If stacked transistor structures are implemented, then integration density improves, but fabrication precision requirements increase
Solution Approach 1:
The patent divides the etching process into multiple discrete steps, each targeting specific depth ranges and structural features. Different etching steps create distinct regions (first channel layers, second channel layers, isolation regions) with controlled depths and profiles. This segmentation of the etching process into manageable stages reduces the precision burden on any single step while achieving the overall complex stacked structure.
Solution Approach 2:
The patent employs preliminary patterning and sacrificial layer formation before final structure definition. Mask layers and sacrificial materials are deposited and patterned in advance to guide subsequent etching steps, ensuring precise alignment and depth control. These preliminary actions establish the geometric framework that guides the multi-step etching process, reducing precision requirements during critical structure formation.
3Manufacturing precision
If multi-step etching processes are used, then transistor profile control improves, but process complexity increases
Solution Approach 1:
The patent applies different etching conditions, selectivities, and depths to different regions of the structure. Each etching step is optimized for its specific target region (e.g., first channel layers vs. second channel layers vs. isolation regions), with tailored process parameters to achieve the desired local profile. This local quality approach allows precise profile control in each region while managing overall process complexity through region-specific optimization.
4Area of stationary object
If vertically stacked transistors are formed, then footprint is reduced, but isolation and electrical control become more difficult
Solution Approach 1:
The patent introduces intermediary isolation layers and sacrificial materials between the n-type and p-type transistor channels. These intermediary structures serve as mediators that provide electrical isolation and mechanical support while enabling the vertical stacking configuration. The isolation layers act as intermediate elements that resolve the conflict between close vertical proximity (for density) and electrical separation (for control), allowing footprint reduction without compromising isolation.
Data Source
AI summary
A method includes a number of operations. A semiconductor stack structure is formed over a substrate, wherein the semiconductor stack structure includes a first semiconductor stack including first channel layers, a second semiconductor stack including second channel layers over the first semiconductor stack and a sacrificial layer between the first and second semiconductor stack. The semiconductor stack structure is etched through, wherein the sacrificial layer is etched such that a top width of the sacrificial layer is different from a bottom width of the sacrificial layer. The etched sacrificial layer is removed. An isolation layer is formed between the first and second semiconductor stacks. First and second source/drain regions are formed on opposite sides of first and second channel layers. First and second gate structures are formed and around the first and second channel layers.