Stacked GAA CFET Power Rail Layout for Lower Cell Height
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Solution Overview
Problem
As semiconductor devices shrink to sub-10-15 nm technology nodes, existing FinFET and GAA FET designs face challenges in minimizing cell height and reducing parasitic via resistance due to the complexity of deep via formation and high aspect ratio contacts, which hinders further scaling and performance improvement.
Innovation Solution
The proposed solution involves a complementary FET (CFET) design where p-type and n-type GAA FETs are vertically stacked, with power supply lines Vdd and Vss positioned at different levels to minimize cell height by eliminating the need for deep contacts and high aspect ratio vias, using a gate dielectric layer and work function adjustment layers to ensure effective control over the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFET or GAA FET designs are used to scale to sub-10-15 nm nodes, then device density and performance are improved, but cell height increases and parasitic via resistance increases due to deep contacts and high aspect ratio structures
Solution Approach 1:
The patent transitions from planar transistor layouts to vertically stacked three-dimensional FET structures (FinFET and GAA FET). By stacking multiple FETs vertically in the third dimension, the device density increases without proportionally increasing the cell height, as the vertical stacking efficiently utilizes the vertical space rather than expanding horizontally.
Solution Approach 2:
The patent implements nested structures where gate electrodes wrap around channel regions in GAA FETs, and multiple FETs are stacked within a compact vertical footprint. The gate-all-around structure nests the gate electrode around the channel, maximizing control while minimizing the horizontal area, thereby improving density without excessive height increase.
2Reliability
If deep contacts and high aspect ratio vias are formed to support vertically stacked FETs, then electrical connectivity is achieved, but manufacturing complexity increases and parasitic via resistance increases
Solution Approach 1:
The patent forms contact holes and via structures at earlier stages of the fabrication process, before the full vertical stack is complete. By preparing the contact pathways in advance and using self-aligned processes, the manufacturing complexity is reduced, and the aspect ratio challenges are mitigated through progressive formation rather than attempting to create all deep contacts simultaneously.
Solution Approach 2:
The patent introduces intermediate contact structures and graded aspect ratio transitions to bridge the connection between upper and lower FETs. These intermediary elements serve as mediators that reduce the effective aspect ratio by creating stepped or tapered transition zones, thereby reducing parasitic resistance without requiring single-step formation of extremely high aspect ratio vias.
Data Source
AI summary
A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.