Stacked GAA Channel Removal for Tight Vertical Device Spacing

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Solution Overview

Problem

In integrated circuit technology, there is a challenge in efficiently forming stacked semiconductor devices with vertically aligned nanoribbons where one device has a continuous channel structure and the other lacks it, while maintaining a small vertical separation between them, which is crucial for achieving high transistor density and operational efficiency.

Innovation Solution

The approach involves forming upper and lower devices with nanoribbons, where one set of nanoribbons is partially removed, and using a sacrificial material and conformal liner to achieve a small vertical separation, allowing for the deposition of gate dielectric and work function metal, and subsequent etching to create a stacked device structure with a continuous gate electrode for one device and a discontinuous gate structure for the other.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If channel regions are removed from stacked devices to increase transistor density, then device complexity increases, but manufacturing precision is maintained through selective etching processes

Engineering Contradiction:
Improvetransistor densityVSAvoiddevice structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The stacked device structure is segmented into upper and lower devices with different channel configurations. The method selectively removes channel regions from either the upper or lower device while preserving channels in the other device, enabling independent optimization of each device's functionality and achieving higher overall transistor density through differentiated device designs

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Sacrificial materials are deposited around the channel regions before the final device formation. These sacrificial materials serve as preliminary structures that guide the selective removal process, ensuring precise channel depopulation in the intended device regions while protecting channels in other devices from being removed

Inventive Principle:
Principle #10Preliminary action

2Productivity

If vertical separation between stacked devices is reduced to increase density, then transistor density improves, but manufacturing precision challenges arise

Engineering Contradiction:
Improvetransistor densityVSAvoidvertical separation control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

Sacrificial materials act as intermediary structures between the upper and lower devices during fabrication. These materials are deposited conformally around the channels and serve as temporary spacers that define the vertical separation distance, enabling precise control of the separation while allowing subsequent selective removal to achieve the desired final configuration

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The vertical separation between devices is controlled by adjusting the thickness and deposition parameters of the sacrificial materials. By changing the physical and chemical parameters of these intermediary layers, the manufacturing process can precisely control the vertical separation distance to optimize both device density and fabrication precision

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20230395678A1Selective removal of channel bodies in stacked gate-all-around (GAA) device structures
Publication Date: 2023.12.07 INTEL CORP
  • US20230395678A1 patent drawing
  • US20230395678A1 patent drawing
  • US20230395678A1 patent drawing

AI summary

A semiconductor structure includes an upper device stacked over a lower device. In an example, the upper device includes (i) a first source region, (ii) a first drain region, (iii) a body of semiconductor material extending laterally from the first source region to the first drain region, and (iv) a first gate structure at least in part wrapped around the body. In an example, the lower device includes (i) a second source region, (ii) a second drain region, and (iii) a second gate structure at least in part laterally between the second source region and the second drain region. In an example, the lower device lacks a body of semiconductor material extending laterally from the second source region to the second drain region. In another example, the upper device lacks a body of semiconductor material extending laterally from the first source region to the first drain region.