Stacked Multi-Gate GAA Structure for Balanced nFET/pFET Currents
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in achieving balanced driving currents from stacked gate-all-around (GAA) transistors, particularly as the number of semiconductor channel layers in n-type and p-type FETs must differ to achieve balanced performance, which existing fabrication methods do not adequately address.
Innovation Solution
The solution involves forming stacked GAA transistors with varying numbers of active channel layers, where at least one stack has floating channel layers, allowing for balanced current driving by adjusting the number of active channel layers in each transistor, and using a common gate structure for both transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same number of semiconductor channel layers are used in both nFET and pFET, then the fabrication process is simplified, but the driving currents become unbalanced
Solution Approach 1:
The patent applies local quality by making the channel layer configuration different for nFET and pFET devices. Specifically, the nFET has a first number of channel layers while the pFET has a second number of channel layers, allowing each device type to be optimized for its specific current driving requirements. This resolves the contradiction by accepting increased fabrication complexity as a necessary trade-off to achieve proper current balancing between nFET and pFET.
Solution Approach 2:
The patent changes the parameter of channel layer count differently for nFET and pFET devices. By varying the number of semiconductor channel layers based on device type, the patent achieves balanced driving currents. This parameter change approach allows the system to optimize performance for each transistor type while maintaining a unified fabrication process framework.
2Reliability
If different numbers of semiconductor channel layers are used in nFET and pFET to balance driving currents, then current balance is achieved, but the fabrication process complexity increases
Solution Approach 1:
The patent segments the channel layer formation process into device-specific stages. Different numbers of channel layers are formed for nFET and pFET through selective epitaxial growth or deposition processes. This segmentation allows independent optimization of each device type's channel structure while using the same overall fabrication methodology, thus managing complexity through systematic process division.
Solution Approach 2:
The patent employs preliminary action by pre-determining the channel layer configuration for each device type before fabrication begins. The different numbers of channel layers are planned and executed as part of the initial device design and fabrication sequence, allowing the complexity to be managed through upfront planning rather than post-fabrication adjustments.
Data Source
AI summary
A semiconductor device according to the present disclosure includes a stack of first channel layers, first and second source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the first channel layers, respectively, a stack of second channel layers stacked over the first channel layers, third and fourth S/D epitaxial features adjacent to opposite sides of at least a portion of the second channel layers, respectively, and a dielectric isolation layer disposed under the first and second S/D epitaxial features. A total active channel layer number of the first channel layers is different from a total active channel layer number of the second channel layers. The dielectric isolation layer is in physical contact with at least a bottommost one of the first channel layers.