Stacked GAA Transistor Vt Patterning With Spin-On Dummy Material
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in fabricating gate structures for gate-all-around (GAA) devices as they continue to scale, leading to degraded performance and increased processing complexity. Additionally, existing complementary field-effect transistors (C-FET) structures are not entirely satisfactory in all aspects, particularly as the industry progresses to smaller technology process nodes.
Innovation Solution
The method involves forming a configuration of a GAA device with vertically stacked transistors, where the top and bottom multi-gate devices are of different conductivity types. This is achieved by depositing a dummy material, such as SiOC or SiOx, using spin-on deposition, and then etching it back to form a uniform dummy material layer. This process allows for selective control of threshold voltages and ensures each transistor in the stack is formed with desired characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If GAA devices continue to scale down to increase device density, then productivity and manufacturing efficiency are improved, but fabrication complexity increases and device performance degrades
Solution Approach 1:
The gate structure is segmented into multiple gates surrounding the channel region from different directions (top, bottom, and sidewalls), creating a gate-all-around configuration. This segmentation allows each gate to independently control the channel, improving device performance while enabling scalable fabrication through modular processing steps
Solution Approach 2:
The invention transitions from planar 2D gate control to 3D gate-all-around control by extending gate structures vertically and laterally to surround the channel region. This dimensional change provides superior electrostatic control and enables continued scaling at smaller technology nodes without proportionally increasing fabrication complexity
2Productivity
If GAA devices continue to scale down, then device density increases, but gate control effectiveness deteriorates
Solution Approach 1:
The gate is divided into multiple segmented gates positioned at different locations (top gate, bottom gate, sidewall gates) that collectively surround the channel. This segmentation ensures that each gate segment maintains effective control over its portion of the channel, preventing short-channel effects even as device dimensions scale down
Solution Approach 2:
The gate structure forms a nested configuration where inner gates are positioned within cavities formed by outer gates, creating a gate-all-around structure. This nested arrangement maximizes gate control by placing gates as close as possible to the channel from all directions, improving electrostatic control at scaled dimensions
3Productivity
If stacked transistor configurations are implemented, then device density increases, but fabrication process complexity increases
Solution Approach 1:
Multiple transistor gates are merged into a single continuous gate-all-around structure that surrounds the channel region. This merging reduces the number of discrete gate components and simplifies the fabrication process by enabling formation of all gates through integrated processing steps rather than separate operations
Solution Approach 2:
Dummy gates are formed in preliminary fabrication steps before the final gate structure is created. These dummy gates serve as templates and sacrificial structures that guide subsequent processing, enabling precise formation of the gate-all-around structure and simplifying later fabrication steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves the performance and reliability of stacked transistor devices by enabling more efficient use of space and enhanced power efficiency, while also simplifying the fabrication process and maintaining effective gate control.
Implementation Method 1
depositing a dummy material, such as SiOC or SiOx, using spin-on deposition
Data Source
AI summary
Methods for forming a stacked transistor device including depositing a dummy material such as by spin-on deposition to process a first transistor differently than a second transistor of the stacked transistor device. Multi-Vt patterning, where different transistors in a stacked device can have different threshold voltages (Vt) can be implemented by depositing a dummy material before patterning to selectively control the Vt of each transistor without affecting the others. In top-bottom FET stacks, by depositing a dummy material, the process can be optimized to ensure that each transistor in the stack is formed with the desired characteristics.