Stacked GAA FET Isolation Layers for Dense SOI Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in increasing device density without aggressively scaling down device dimensions, which complicates fabrication and increases costs, particularly due to the need for electrical isolation between devices in integrated circuits.
Innovation Solution
The use of stacked gate-all-around (GAA) FETs with a FET isolation layer, including channel and source/drain isolation layers, allows for increased device density without compromising electrical isolation, and forming these FETs on a silicon-on-insulator (SOI) substrate eliminates the need for shallow trench isolation regions, simplifying the fabrication process and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are scaled down to increase device density, then device density increases, but fabrication complexity increases and costs increase
Solution Approach 1:
The patent transitions from planar device layout to three-dimensional stacked FET architecture, stacking multiple FETs vertically on a single footprint. This dimensional change increases device density without requiring further scaling of individual device dimensions, thereby avoiding the associated fabrication complexity and cost increases.
Solution Approach 2:
The patent divides the device structure into distinct stacked layers, with each FET comprising separate source, channel, and drain regions arranged vertically. This segmentation allows for modular fabrication processes and simplifies the manufacturing of high-density devices by enabling standardized layer-by-layer construction.
2Reliability
If conventional planar FETs with shallow trench isolation are used, then electrical isolation is achieved, but fabrication process complexity increases
Solution Approach 1:
The patent extracts and eliminates the shallow trench isolation (STI) structure from the fabrication process by implementing FETs directly on an SOI substrate. The buried oxide layer of the SOI substrate provides the necessary electrical isolation between devices, removing the need for additional STI formation steps and simplifying the overall fabrication process.
3Ease of manufacture
If stacked FETs on SOI substrate are implemented, then fabrication process is simplified and costs are reduced, but electrical isolation must be maintained
Solution Approach 1:
The patent utilizes the buried oxide layer of the SOI substrate as an intermediary isolation layer between stacked FETs. This oxide layer serves as an effective electrical barrier, maintaining proper isolation between devices while enabling simplified fabrication processes without requiring additional isolation structures.
Data Source
AI summary
A semiconductor device and methods of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure with first and second nanostructured layers on the fin structure, forming a polysilicon structure around the superlattice structure, forming a source/drain opening within the superlattice structure, forming a first conductivity type S/D region within a first portion of the S/D opening, forming an isolation layer on the first conductivity type S/D region and within a second portion of the S/D opening, forming a second conductivity type S/D region on the isolation layer and within a third portion the S/D opening, and replacing the polysilicon structure and the second nanostructured layers with a gate structure that surrounds the first nanostructured layers. Materials of the first and second nanostructured layers are different from each other and the second conductivity type is different from the first conductivity type.