Stacked GAA Logic and I/O Circuits for Mixed Gate Oxide Thickness
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Solution Overview
Problem
Advanced semiconductor manufacturing techniques face integration challenges due to differing voltage requirements between core and non-core circuits in GAA transistor-based devices, where the non-core circuits need thicker gate dielectric materials incompatible with the narrow gaps in GAA transistors.
Innovation Solution
Separate manufacturing process nodes are assigned to core and non-core circuits, with GAA transistors on one wafer and nGAA transistors on another, allowing for thicker gate dielectric layers in non-core circuits without compromising the advanced computing capabilities of GAA transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If non-core circuits use thicker gate dielectric material to meet large voltage drop requirements, then voltage handling capability is improved, but the limited inter-nanosheet spacing in GAA transistors cannot accommodate the thick gate dielectric material
Solution Approach 1:
The patent divides the semiconductor device into two separate substrates: one for core circuits using GAA transistors with thin gate dielectric, and another for non-core circuits using planar or fin-type transistors with thick gate dielectric. This segmentation allows each substrate to be optimized independently for its specific voltage requirements, resolving the contradiction between voltage handling capability and inter-nanosheet spacing constraints.
Solution Approach 2:
The patent transitions from a single-substrate three-dimensional integration approach to a multi-substrate stacked architecture. By moving the non-core circuits to a separate substrate and bonding it to the GAA substrate, the solution adds a dimensional aspect (vertical stacking of substrates) that accommodates both thin and thick gate dielectric requirements without interfering with the inter-nanosheet spacing in GAA transistors.
2Productivity
If GAA transistors are used in core circuits for high speed and low power, then computing performance is improved, but integration with non-core circuits becomes difficult due to different voltage requirements
Solution Approach 1:
The patent segments the device into dedicated core circuit substrate and non-core circuit substrate, allowing GAA transistors to achieve high computing performance in core circuits without compromising non-core circuit functionality. This segmentation simplifies integration by allowing each substrate to be manufactured and optimized independently before final assembly.
Solution Approach 2:
The patent introduces a bonding interface as an intermediary between the GAA substrate and non-core circuit substrate. This bonding interface serves as a mediator that connects the two different transistor technologies, enabling them to work together despite their different voltage requirements and structural characteristics.
3Area of stationary object
If a single substrate is used for both core and non-core circuits, then device area is reduced, but the different gate dielectric thickness requirements cannot be simultaneously satisfied
Solution Approach 1:
The patent resolves the area constraint by utilizing the vertical dimension through substrate stacking. Instead of competing for horizontal space on a single substrate, the core and non-core circuits are placed on separate substrates that are bonded together vertically, effectively using the third dimension to accommodate both circuit types with their different gate dielectric requirements.
Solution Approach 2:
By segmenting the device into multiple substrates, the patent enables each substrate to have gate dielectric thickness specifically adapted to its circuit type, thereby achieving gate dielectric thickness adaptability while the overall device footprint remains compact due to the stacked architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed, low-power core circuits with non-core circuits capable of sustaining higher operating voltages, reducing integration complexity and production costs while maintaining reliability.
Implementation Method 1
a gate silicon oxide layer of each of the GAA-type transistors has a third thickness. The third thickness is less than the first thickness or the second thickness
Data Source
AI summary
A semiconductor device includes a first substrate and a second substrate. The first substrate has a plurality of first-type transistors formed of planar-type transistors or fin-type transistors, wherein a gate silicon oxide layer of each of the planar-type transistors has a first thickness, and a gate silicon oxide layer of each of the fin-type transistors has a second thickness. The second substrate is bonded to the first substrate and including a plurality of second-type transistors formed of gate-all-around (GAA) transistors, wherein a gate silicon oxide layer of each of the GAA transistors has a third thickness. The third thickness is less than the first thickness or the second thickness.