Stacked-Channel GAA Gate Formation for Meta-Gate Height Control
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Solution Overview
Problem
The conventional meta-gate etching-back process for semiconductor fabrication faces challenges in controlling and reducing the final meta-gate height due to variations in etching processes across different meta-gate layers and spacing loading, which complicates the manufacturing of three-dimensional designs like multi-gate field effect transistors.
Innovation Solution
A method involving the formation of fin structures using alternately stacked semiconductor layers, followed by the creation of sacrificial gate structures and gate spacers, and subsequent etching processes to define source/drain regions and recesses, allowing for precise control over the meta-gate height through selective etching and deposition techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional meta-gate etching-back process is used, then manufacturing process is simple, but final meta-gate height control precision deteriorates due to etching process variations
Solution Approach 1:
The patent segments the meta-gate formation process into multiple distinct stages: initial meta-gate layer deposition, selective etching to form recesses, and subsequent meta-gate material deposition. This segmentation allows each stage to be optimized independently, with the selective etching step creating precise depth control for the final meta-gate height, thereby resolving the contradiction between manufacturing precision and process complexity.
Solution Approach 2:
The patent employs preliminary action by forming sacrificial layers and performing selective etching before final meta-gate deposition. The sacrificial layers are deposited and patterned in advance to define the precise locations and depths where meta-gate material will later be deposited, ensuring accurate height control before the actual meta-gate formation occurs.
2Adaptability or versatility
If multiple meta-gate layers with different spacing are used, then device functionality is enhanced, but etching process uniformity deteriorates due to spacing loading variations
Solution Approach 1:
The patent applies local quality by making the etching process selective to specific regions based on spacing. The selective etching step targets only certain meta-gate layer regions while leaving others intact, allowing different spacing configurations to coexist without compromising overall etching uniformity. This regional selectivity enables versatile device functionality while maintaining process precision.
3Productivity
If meta-gate height is reduced for higher device density, then device density increases, but etching process control becomes more difficult
Solution Approach 1:
The patent introduces sacrificial layers as intermediary elements that mediate between the etching process and the final meta-gate structure. These sacrificial layers act as temporary placeholders that define the precise geometry needed for the final reduced-height meta-gate, allowing the etching process to work at relaxed dimensions while achieving the desired final compact structure through subsequent removal of the sacrificial material.
Data Source
AI summary
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes channel layers, a mask structure, a gate structure and a source/drain pattern. The channel layers are stacked vertically apart along a first direction over a substrate. The mask structure is disposed over and apart from the channel layers along the first direction. The gate structure laterally extends along a second direction perpendicular to the first direction disposed, wherein the gate structure wraps around the channel layers and laterally surround the mask structure. The source/drain pattern is in contact with the channel layers.