Self-Aligned Stacked GAA Nanosheets for Hybrid nFET/pFET Integration
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Solution Overview
Problem
Current semiconductor technologies face challenges in integrating nanosheet channels on different substrate crystallization structures for high-performance applications, particularly in reducing process integration complexity and enhancing carrier mobility, while existing non-planar devices like FinFETs have limitations in gate length scaling and substrate orientation.
Innovation Solution
A vertically stacked gate-all-around (GAA) semiconductor device is developed, comprising self-aligned nanosheet channels with different crystalline orientations for nFET and pFET, where the second vertical stack of nanosheet channels has sidewalls self-aligned to the first, and an insulator material bonding layer is used between the gate structures, enabling easier integration and improved carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separate co-planar nFETs and pFETs are used on hybrid substrates, then device functionality is achieved, but integration complexity increases and alignment difficulty worsens
Solution Approach 1:
The patent transitions from co-planar (2D) device arrangement to vertically stacked (3D) configuration, where nFET and pFET are stacked one above the other along the vertical dimension. This dimensional change enables better space utilization, simplified standard cell alignment, and reduced integration complexity while maintaining device functionality.
Solution Approach 2:
The patent merges the nFET and pFET structures into a single vertically integrated stack, combining what were previously separate co-planar devices into one unified three-dimensional structure. This merging reduces the number of separate alignment operations and simplifies the overall integration process.
2Ease of manufacture
If traditional FinFET structures are used, then manufacturing is simpler, but gate length scaling is limited
Solution Approach 1:
The patent employs gate-all-around (GAA) structures where the gate completely surrounds the channel in three dimensions, including vertical sidewalls. This 3D gate configuration provides superior electrostatic control compared to planar gates, enabling effective gate length scaling to smaller dimensions while maintaining manufacturability through self-aligned processes.
Solution Approach 2:
The gate structure is nested around the channel region, with the gate wrapping completely around the channel in a surrounding configuration. This nested GAA structure provides enhanced control over the channel while enabling continued scaling of the effective gate length.
3Reliability
If nanosheet channels with different crystalline orientations are integrated, then carrier mobility is enhanced, but process integration complexity increases
Solution Approach 1:
The patent assigns different crystalline orientations to specific device types within the stack: (100) orientation for nFET channels and (110) orientation for pFET channels. This local differentiation of material properties optimizes carrier mobility for each device type while the self-aligned fabrication process manages the integration complexity.
Solution Approach 2:
The self-aligned fabrication process automatically ensures precise alignment between the nFET and pFET nanosheet stacks without requiring additional alignment steps. The process structure itself provides the alignment, eliminating the need for complex external alignment procedures and reducing overall process integration complexity.
4Ease of manufacture
If vertically stacked GAA structure is implemented, then integration is easier and alignment is simpler, but manufacturing precision requirements increase
Solution Approach 1:
The self-aligned fabrication process uses the device structures themselves as alignment references. Previous layers and features automatically define the positions of subsequent layers, eliminating the need for separate alignment operations and reducing sensitivity to alignment precision requirements while maintaining ease of integration.
Solution Approach 2:
The fabrication process performs preliminary formation of reference structures and alignment features before final device assembly. By establishing alignment references early in the process, subsequent steps inherit this precision without requiring additional high-precision alignment operations.
Data Source
AI summary
A semiconductor structure including vertically stacked nFETs and pFETs containing suspended semiconductor channel material nanosheets (NS) and a method of forming such a structure. The structure is a three dimensional (3D) integration by vertically stacking nFETs and pFETs for area scaling. In an embodiment, vertically-stacked NS FET structures include a first nanosheet transistor located above a second nanosheet transistor; the first nanosheet transistor including a first NS channel material, wherein the first NS channel material includes a first crystalline orientation; the second nanosheet transistor including a second NS channel material, wherein the second NS channel material comprises a second crystalline orientation, the first crystalline orientation is different from the second crystalline orientation. In an embodiment, each of the respective formed vertically-stacked NS FET structures include respective suspended stack of nanosheet channels that are self-aligned with each other.