Vertically Stacked GAA Transistors With Suspended Oxide Channels
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes is exacerbated by the increasing complexity and difficulty of fabrication processes as feature sizes continue to decrease, necessitating improved manufacturing techniques for semiconductor integrated circuits.
Innovation Solution
The use of gate all around (GAA) transistor structures, patterned through photolithography and self-aligned processes, combined with sacrificial layers and spacer formation, allows for the creation of vertically stacked transistors with alternating semiconductor and sacrificial layers, enabling precise patterning and etching to form suspended channel layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process difficulty increases
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional vertically stacked GAA transistor structures. This dimensional change allows continued scaling and increased functional density while maintaining manufacturability by distributing the complexity across multiple vertical layers rather than compressing features in a single plane.
Solution Approach 2:
The patent divides the transistor structure into multiple discrete layers including alternating semiconductor and sacrificial layers, gate structures, and spacer regions. This segmentation enables precise control and fabrication of each layer independently, making the overall complex structure more manageable and manufacturable.
2Productivity
If feature sizes continue to decrease, then functional density increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
The patent employs sacrificial layers that are formed and patterned before the final semiconductor structure is complete. These preliminary sacrificial structures serve as templates and placeholders that guide subsequent fabrication steps, ensuring precise positioning and dimensions are achieved in the final device.
Solution Approach 2:
The patent uses spacer layers as intermediary structures that are formed between the sacrificial layers and the final semiconductor features. These spacers act as mediators that transfer the pattern from the sacrificial layers to the final structure, enabling precise feature formation at reduced dimensions through self-aligned processes.
3Productivity
If vertically stacked GAA transistor structures are formed, then integration density is improved, but process complexity increases
Solution Approach 1:
The patent implements a nested structure where gate structures surround semiconductor channels in a gate-all-around configuration, and multiple transistor layers are stacked vertically within a compact footprint. This nesting approach maximizes integration density by efficiently utilizing three-dimensional space while organizing complex components in a hierarchical manner.
Solution Approach 2:
The patent uses sacrificial layers that serve multiple functions: they act as placeholders during fabrication, define the pattern for subsequent spacer formation, and are eventually removed to create the final suspended channel structure. This multi-functionality reduces process complexity by combining multiple steps into a unified approach.
Data Source
AI summary
A method includes forming first sacrificial layers and first channel layers alternately stacked over a substrate; forming second channel layers and second sacrificial layers alternately stacked over the first sacrificial layers and the first channel layers, in which the second channel layers are made of a first semiconductive oxide; performing an etching process to remove portions of the first sacrificial layers and the second sacrificial layers; forming a gate structure in contact with the first channel layers and the second channel layers; forming first source/drain contacts on opposite sides of the gate structure and electrically connected to the first channel layers; and forming second source/drain contacts on the opposite sides of the gate structure and electrically connected to the second channel layers.