Stacked GAA Transistor Power Layout for Lower Cell Height
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Solution Overview
Problem
As integrated circuits become smaller, there is a need to further reduce the area occupied by the layout and improve the routing flexibility while maintaining effective power grid distribution.
Innovation Solution
The solution involves a configuration where a first transistor with a gate-all-around (GAA) structure is stacked over a second transistor, with power lines VDD and VSS disposed on opposite sides of the transistors. The power line VSS has a larger area than VDD, enhancing routing flexibility and reducing cell height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the area of the layout is decreased by substituting new structures and reducing distance between circuit elements, then the overall area occupied by the integrated circuit is reduced, but the routing flexibility and power grid distribution effectiveness deteriorate
Solution Approach 1:
The patent transitions from planar routing to three-dimensional routing by stacking power lines VDD and VSS vertically over active regions. This vertical arrangement in the third dimension enables effective power grid distribution while maintaining reduced lateral distances between circuit elements, thus preserving routing flexibility without increasing layout area.
Solution Approach 2:
The patent implements nested power line structures where power lines VDD and VSS are stacked vertically one over the other, with each power line having different widths. The larger width power line is positioned to accommodate routing needs while the smaller width power line optimizes power distribution, creating a nested configuration that maximizes both routing flexibility and power grid effectiveness within constrained area.
2Ease of manufacture
If power lines are configured with equal widths for symmetry, then manufacturing simplicity is maintained, but routing flexibility and power grid distribution effectiveness are limited
Solution Approach 1:
The patent deliberately employs asymmetric power line widths where one power line (VSS or VDD) has a larger width than the other. This asymmetry is strategically configured to enhance routing flexibility and improve power grid distribution effectiveness. The different widths allow optimized current distribution and routing paths while maintaining manufacturing feasibility through standard fabrication processes.
3Productivity
If the distance between circuit elements is reduced to increase density, then the layout area decreases, but manufacturing precision and reliability deteriorate
Solution Approach 1:
The patent resolves the precision-density tradeoff by moving power line routing to the vertical dimension through stacking. This allows circuit elements to be positioned closer together in the lateral plane (increasing density) while power lines are routed vertically above active regions, maintaining adequate spacing and alignment margins that preserve manufacturing precision despite reduced element distances.
Data Source
AI summary
An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.