Stacked GAA Transistor Fabrication With Selective Sacrificial Etching
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Solution Overview
Problem
The existing methods for manufacturing 3D architectures based on Gate-all-around (GAA) transistors are complex and costly, requiring multiple transfer steps and high thermal budgets, which complicates the production of stacked transistors for advanced microelectronic devices.
Innovation Solution
A method involving the formation of a stack with sacrificial layers, followed by the creation of transistor patterns, sacrificial gates, and selective etching to insulate and fill spaces with dielectric material, allowing for the formation of GAA transistors with gates completely surrounding the channels, reducing complexity and cost by eliminating the need for layer transfers and minimizing thermal stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple transfer steps and molecular bonding are used to construct stacked GAA transistors, then gate confinement is improved, but device complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent applies preliminary action by pre-forming complete GAA transistor stacks with all necessary components (channels, gates, sources, drains) in a single epitaxial growth step before any separation or transfer operations. The sacrificial layers are pre-integrated into the stack structure during this initial formation, enabling subsequent simple separation without complex assembly steps.
Solution Approach 2:
The patent merges multiple manufacturing operations into a single epitaxial growth step, where alternating layers of semiconductor material and sacrificial material are grown simultaneously to form the complete transistor stack structure. This consolidation eliminates the need for separate transfer and bonding steps for each transistor layer.
2Reliability
If multiple transfer steps are performed to construct stacked GAA transistors, then gate confinement is improved, but thermal budget management becomes more difficult
Solution Approach 1:
The patent performs the high-temperature epitaxial growth step before any separation or transfer operations. By completing the structural formation while thermal budget is available, the method avoids subsequent high-temperature processing that would be required for bonding separate layers, thus simplifying thermal budget management.
3Device complexity
If sacrificial layers are removed and spaces filled with dielectric material, then manufacturing complexity is reduced, but additional processing steps are required
Solution Approach 1:
The patent extracts the sacrificial layers from the transistor stack through selective removal processes. This extraction creates voids that are subsequently filled with dielectric material to form the final transistor structure with proper electrical isolation, simplifying the overall manufacturing by eliminating the need for complex layer-by-layer assembly.
Data Source
AI summary
A device includes gate-all-around transistors and method for manufacturing such a device. A method for manufacturing a microelectronic device includes at least two transistors each comprising a channel in the shape of a wire extending in a first direction x, a gate surrounding said channel, a source and a drain, said transistors being stacked in a third direction z and each occupying a level nz (z=1 . . . 4) of given altitude in the third direction z.