Stacked GAA Transistor Doping for Low-Power IC Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuit (IC) manufacturing while managing increasing power dissipation, which requires innovative approaches to maintain efficiency and reduce costs.
Innovation Solution
The method involves forming gate all around (GAA) transistor structures using epitaxial stacks with sacrificial and channel layers, selective etching, and high-k/metal gate replacement, allowing for precise control of channel dimensions and doping to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then productivity and production efficiency are improved, but power dissipation increases
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional vertically-stacked channel structures. Multiple channel layers are stacked vertically to increase functional density without increasing chip area, while the vertical stacking enables better power management and reduced power dissipation through improved device architecture
Solution Approach 2:
The transistor channel is divided into multiple discrete channel layers stacked vertically, with each layer potentially having different doping concentrations and material compositions. This segmentation allows independent optimization of each layer for specific functions, enabling low-power operation while maintaining high density
2Productivity
If functional density is increased through scaling down, then productivity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary patterning and epitaxial growth steps to pre-form the stacked channel structures and sacrificial layers before final device fabrication. This preliminary structuring simplifies subsequent processing steps and enables high-density structures to be manufactured with controlled complexity
Solution Approach 2:
The patent utilizes changes in material parameters during epitaxial growth, including varying doping concentrations, layer thicknesses, and material compositions across different channel layers. These parameter variations enable precise control of device characteristics while maintaining manufacturing feasibility through standardized epitaxial processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of high-density, low-power ICs by optimizing channel geometry and doping, enhancing manufacturing efficiency and reducing power dissipation.
Implementation Method 1
performing a first ion implantation process to form a first lightly doped region adjoining the first channel layer; performing a second ion implantation process to form a second lightly doped region adjoining the second channel layer
Implementation Method 2
forming a first epitaxial stack over a substrate, the first epitaxial stack comprising a first sacrificial layer and a first channel layer over the first sacrificial layer; forming a second epitaxial stack over the first epitaxial stack, the second epitaxial stack comprising a second sacrificial layer and a second channel layer over the second sacrificial layer
Data Source
AI summary
A method for fabricating an integrated circuit device includes forming first epitaxial stack comprising a first sacrificial layer and a first channel layer over a substrate; forming a second epitaxial stack comprising a second sacrificial layer and a second channel layer over the first epitaxial stack; etching a recess in the first and second epitaxial stacks, wherein the recess exposes end surfaces of the first and second channel layers; performing a first ion implantation process to form a first lightly doped region; performing a second ion implantation process to form a second lightly doped region, wherein a tilt angle of the second ion implantation process is greater than a tilt angle of the first ion implantation process; forming first and second source/drain epitaxial features in the recess; and replacing the first and the second sacrificial layers with a high-k/metal gate structure.