Stacked GAA Transistor Structure for Integration and Gate Control
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices has led to challenges in enhancing the integration and electrical properties of planar metal oxide semiconductor field effect transistors (FETs), particularly due to size reduction limitations, necessitating the development of advanced semiconductor structures like FinFETs and gate-all-around field effect transistors.
Innovation Solution
A semiconductor device design featuring vertically stacked complementary field effect transistors with channel layers having varying impurity concentrations of carbon (C) and oxygen (O) along their height, and gate electrodes surrounding these channel layers, which include source/drain regions and gate dielectric layers, enhancing electrical properties and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar metal oxide semiconductor FETs are used to increase integration, then device density improves, but electrical properties deteriorate due to size reduction limitations
Solution Approach 1:
The patent transitions from planar 2D channel structures to vertically stacked 3D channel structures (FinFET and nanosheet configurations). This dimensional change allows the channel to extend into the vertical dimension, increasing effective channel width and drive current without increasing planar footprint, thereby maintaining electrical performance while achieving higher integration density.
Solution Approach 2:
The patent implements gate-all-around structures where the gate electrode completely surrounds the channel structure (nanosheets or fin) on all sides. This nested configuration provides maximum gate control over the channel, enabling effective electrostatic control and carrier modulation even at scaled dimensions, thus maintaining electrical properties while achieving size reduction for higher integration.
2Length of moving object
If channel layer width is reduced for size scaling, then device footprint decreases, but gate control and electrical performance worsen
Solution Approach 1:
The patent compensates for reduced planar channel width by extending the channel into the vertical dimension through FinFET structures or multiple stacked nanosheets. This increases the effective channel volume and drive current capability while maintaining scaled planar dimensions, thus achieving size reduction without sacrificing electrical performance.
Solution Approach 2:
The gate electrode is configured to completely surround the channel structure (nanosheets or fin) in a gate-all-around arrangement. This provides 360-degree gate control, maximizing the electric field coverage and carrier modulation efficiency even when the channel dimensions are scaled down, thereby maintaining excellent gate control at reduced sizes.
3Productivity
If vertically stacked transistor structures are implemented, then integration density improves, but device complexity increases
Solution Approach 1:
The patent stacks multiple transistor channels vertically to increase the effective channel width without increasing planar footprint. This vertical stacking achieves higher integration density while using standardized fabrication processes adapted for 3D structures, managing complexity through process reuse rather than fundamentally new manufacturing techniques.
Solution Approach 2:
The gate electrode is formed to completely surround the vertical channel structures (nanosheets or fin) in a nested gate-all-around configuration. This unified gate structure simplifies the control mechanism compared to multiple separate gates, as a single gate voltage can modulate all stacked channels simultaneously, thereby managing device complexity while achieving high integration.
Data Source
AI summary
A semiconductor device includes a first transistor structure on a substrate, the first transistor structure including first channel layers spaced apart from each other, a first gate electrode surrounding the first channel layers, a first source/drain region connected to the first channel layers on a first side of the first gate electrode, and a second source/drain region connected to the first channel layers on a second side of the first gate electrode that is opposite to the first side of the first gate electrode, and a second transistor structure on the first transistor structure, the second transistor structure including second channel layers spaced apart from each other, a second gate electrode surrounding the second channel layers, and a third source/drain region connected to the second channel layers on a first side of the second gate electrode.