Stacked GAA Transistor Layout for Higher Device Density
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuit (IC) manufacturing while maintaining complexity and efficiency, requiring advancements in processing and manufacturing techniques to accommodate smaller geometries and increased functional density.
Innovation Solution
The method involves forming gate-all-around (GAA) transistor structures using a multi-patterning process, including the use of sacrificial layers, epitaxial growth, and self-aligned spacers to create nanowire or bar-shaped channels surrounded by a contiguous gate structure, allowing for the formation of stacked horizontal GAA devices with improved density and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional single-patterning processes are used, then manufacturing process is simpler, but device density and functional complexity cannot be increased
Solution Approach 1:
The patent applies multi-patterning processes that divide the patterning operation into multiple sequential steps, each creating a portion of the final pattern. This segmentation enables higher device density by creating more intricate circuit layouts than single-patterning can achieve, while managing complexity through systematic process breakdown into manageable stages
Solution Approach 2:
The patent employs three-dimensional transistor structures including gate-all-around (GAA) configurations and vertically stacked devices. This dimensional transition from planar to vertical architecture increases functional density and device complexity without proportionally increasing layout area, resolving the contradiction between density improvement and processing complexity
2Productivity
If geometry size is decreased, then production efficiency increases and costs降低, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes self-aligned spacer formation where spacers automatically position themselves relative to patterned features without additional alignment steps. This self-service mechanism maintains manufacturing precision at reduced geometry sizes by eliminating alignment errors that would otherwise accumulate through multiple lithography steps
Solution Approach 2:
The patent employs epitaxial growth processes that precisely control crystal structure and material composition at the nanoscale. By controlling parameters such as temperature, pressure, and gas flow during epitaxial deposition, the process achieves high manufacturing precision for three-dimensional transistor structures despite reduced geometry dimensions
3Productivity
If functional density is increased, then IC capability improves, but layout area decreases requiring more complex structures
Solution Approach 1:
The patent implements vertically stacked three-dimensional transistor devices that extend functionality into the vertical dimension. Multiple transistor channels are stacked above each other, increasing functional density without proportionally increasing planar layout area, as the vertical stacking accommodates more devices within the same footprint
Solution Approach 2:
The patent employs gate-all-around structures where the gate electrode completely surrounds the channel region in three dimensions. This nested configuration maximizes the electric field control and functional density within the available space, allowing higher device complexity without linearly increasing layout area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of densely packed, complex semiconductor devices with increased device density and reduced layout area, facilitating the production of smaller, more efficient ICs.
Implementation Method 1
the use of sacrificial layers, epitaxial growth, and self-aligned spacers to create nanowire or bar-shaped channels
Data Source
AI summary
A semiconductor device includes a first device formed over a substrate. The first device includes a first device formed over a substrate, and the first device includes a first gate stack structure encircling a plurality of first nanostructures. The semiconductor device includes a first epitaxy structure wrapping an end of one of the first nanostructures, and a second device formed over the first device, wherein the second device includes a second gate stack structure encircling a plurality of second nanostructures. The semiconductor device includes a second epitaxy structure wrapping an end of one of the second nanostructures, and the second epitaxy structure is directly above the first epitaxy structure.