Stacked Gate-All-Around Transistors for Lithography-Limited Scaling
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in scaling multi-gate and nanowire transistors, where the reduction in device dimensions and increased density lead to constraints in lithographic processes, particularly in achieving optimal critical dimension and spacing, and integrating different channel materials for stacked transistor structures.
Innovation Solution
The use of gate-all-around integrated circuit structures with stacked architectures, employing SOI-like substrates and sequential epi-layer processing, and self-aligned bottom-up oxidation for nanowire transistor channel depopulation, allows for the integration of different channel materials and modulation of drive currents by varying the number of active nanowires or nanoribbons, enabling enhanced density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are reduced and density is increased, then capacity and functional unit density are improved, but lithographic process constraints worsen
Solution Approach 1:
The patent transitions from planar 2D transistor architectures to three-dimensional vertically-stacked architectures. By stacking multiple transistor layers vertically, the design achieves higher functional unit density without proportionally increasing lithographic complexity, as the vertical stacking can be achieved through sequential deposition and patterning processes rather than requiring proportionally smaller lateral feature sizes.
Solution Approach 2:
The patent divides the transistor structure into multiple stacked layers, with each layer containing nanowire channels and gate structures. This segmentation allows the complex three-dimensional structure to be fabricated through sequential processing steps, where each layer can be formed and patterned independently, thereby managing lithographic complexity while achieving high density.
2Length of moving object
If critical dimension is reduced, then device size is reduced, but spacing between features becomes constrained
Solution Approach 1:
The patent utilizes vertical stacking to achieve device miniaturization. By forming multiple transistor layers stacked vertically with controlled spacing, the design reduces the lateral footprint while maintaining adequate spacing between features through the vertical dimension. The gate-all-around structures enveloping nanowire channels in three dimensions further enable compact integration while preserving necessary feature spacing for fabrication.
3Device complexity
If nanowire channels are released and etched, then gate-all-around structures are formed, but process complexity increases
Solution Approach 1:
The patent employs a replacement gate methodology where dummy gates are formed preliminarily before nanowire release and final gate structure formation. This preliminary action provides structural support during the nanowire release process and enables subsequent gate-all-around structure formation without requiring complex simultaneous operations. The dummy gates are later removed and replaced with the final gate materials, simplifying the overall process sequence.
Solution Approach 2:
The patent uses dummy gates as intermediary structures during fabrication. These temporary structures facilitate the release and handling of suspended nanowire channels, providing mechanical support during processing. The dummy gates serve as intermediaries that are eventually removed and replaced with the functional gate-all-around structures, thereby enabling complex device formation through simpler sequential steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of high-density, high-performance nanowire and nanoribbon-based CMOS architectures with improved drive currents and reduced leakage, facilitating more aggressive scaling and efficient interconnect integration without the need for extreme lithographic patterning or aggressive etches.
Implementation Method 1
selected portions of the vertical arrangement of nanowires are released and a gate stack is formed over the vertical arrangement of nanowires. The selected portions of the vertical arrangement of nanowires have an oxidation catalyst layer thereon.
Data Source
AI summary
Gate-all-around integrated circuit structures having stacked architectures, and methods of fabricating gate-all-around integrated circuit structures having stacked architectures, are described. For example, an integrated circuit structure includes a first transistor having a first plurality of nanowires of a first composition. A second transistor having a second plurality of nanowires is vertically over and spaced apart from the first plurality of nanowires, the second plurality of nanowires of a second composition different than the first composition. An oxide layer is completely vertically separating the first transistor from the second transistor or an oxide layer only partially vertically separating the first transistor from the second transistor.