Stacked GAA Transistor Vt Patterning With Spin-On Dummy Mask
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Challenges arise in fabricating gate structures for gate-all-around (GAA) devices and stacked complementary field effect transistors (C-FET) due to increased complexity and degradation of device performance during the scaling process, which affects process control and device reliability.
Innovation Solution
The method involves depositing a dummy material, such as a carbon-based dielectric, using spin-on deposition to form a uniform layer within openings in the device structure, which is then etched back to mask specific regions, allowing for precise control of transistor characteristics and optimizing the stacking process of transistors with different threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If GAA devices are scaled down to increase device density, then productivity and cost efficiency are improved, but manufacturing complexity increases and device performance degrades
Solution Approach 1:
The fabrication process is divided into separate loops: a first fabrication loop forms the lower transistor with its gate structure, and a second fabrication loop forms the upper transistor with its gate structure. This segmentation allows each transistor to be independently optimized and fabricated, reducing overall manufacturing complexity while maintaining high device density.
Solution Approach 2:
A dummy gate structure is formed in advance over the channel region before the actual gate structures are created. This preliminary structure serves as a template and protection layer during subsequent processing steps, simplifying the fabrication of the final gate-all-around structures while enabling aggressive scaling.
2Productivity
If GAA devices are scaled down to increase device density, then productivity is improved, but device performance deteriorates
Solution Approach 1:
The method enables different gate structures to be formed for upper and lower transistors within the same stacked device. The lower transistor can have a gate structure optimized for one type of operation while the upper transistor has a gate structure optimized for another type, allowing each transistor to maintain high performance despite overall device scaling.
Solution Approach 2:
The fabrication process allows for changing gate structure parameters between the first and second transistors. Different gate materials, thicknesses, or configurations can be implemented in each transistor to optimize performance characteristics while maintaining compatibility with scaled device dimensions.
3Productivity
If stacked C-FET structures are used to increase device density, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The stacked C-FET device is fabricated in separate loops where the first transistor and second transistor are formed independently. This segmentation relaxes manufacturing precision requirements by allowing each transistor to be optimized separately rather than requiring perfect symmetry and matching in a single monolithic structure.
Solution Approach 2:
Instead of forming a single symmetric gate structure for both transistors, the method inverts the conventional approach by forming different gate structures for the upper and lower transistors. This inversion allows each transistor to be tailored for its specific function (n-type or p-type), improving performance while reducing the stringency of manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the flexibility and reliability of transistor performance by enabling tailored threshold voltage control and improved process control, leading to optimized device characteristics in stacked transistor configurations.
Implementation Method 1
depositing a dummy material, such as a carbon-based dielectric, using spin-on deposition to form a uniform layer within openings in the device structure
Implementation Method 2
which is then etched back to mask specific regions
Data Source
AI summary
Methods for forming a stacked transistor device including depositing a dummy material such as by spin-on deposition to process a first transistor differently than a second transistor of the stacked transistor device. Multi-Vt patterning, where different transistors in a stacked device can have different threshold voltages (Vt) can be implemented by depositing a dummy material before patterning to selectively control the Vt of each transistor without affecting the others. In top-bottom FET stacks, by depositing a dummy material, the process can be optimized to ensure that each transistor in the stack is formed with the desired characteristics.