Stacked GAAFET IC Structure with Buried Wire Interconnects
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Solution Overview
Problem
Conventional integrated circuit (IC) structures with stacked field effect transistors (FETs) face complexity in providing power and/or signal connections to the source/drain regions, which limits area savings and scalability.
Innovation Solution
The IC structure incorporates stacked pairs of gate-all-around field effect transistors (GAAFETs) with buried wires and embedded contacts within an isolation region, enabling efficient power and signal connections by reducing the number of metal tracks required, and facilitating size scaling by allowing for more compact layouts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If stacked pairs of FETs are used to reduce chip area, then area savings are achieved, but providing power and signal connections to source/drain regions becomes complex
Solution Approach 1:
The patent transitions from planar metal track connections to three-dimensional embedded contacts and buried wires within the isolation region. By utilizing the vertical dimension and subsurface routing, power and signal connections are established without requiring additional lateral metal track layers, thus maintaining area savings while reducing connection complexity
Solution Approach 2:
The patent introduces embedded contacts as intermediary elements that bridge the source/drain regions to buried wires within the isolation region. These embedded contacts serve as mediators that simplify the connection architecture by providing direct electrical pathways without requiring complex metal track arrangements
2Area of stationary object
If conventional metal track arrangements are used for connections, then power and signal connections are provided, but area savings are limited
Solution Approach 1:
The patent merges the isolation region with the connection infrastructure by embedding wires and contacts within the isolation region itself. This combining of functions allows the isolation region to serve dual purposes: electrical isolation and interconnect routing, thereby reducing the total chip area required while maintaining manufacturing feasibility
Data Source
AI summary
Disclosed are integrated circuit (IC) structure embodiments that incorporate stacked pair(s) of field effect transistors (FETs) (e.g., gate-all-around FETs), including a lower FET and an upper FET on the lower FET, and various metal components that enable power and/or signal connections to the source/drain regions of those FETs. The metal components can include first buried wire(s) within an isolation region in a level below the stacked pair and a first embedded contact that electrically connects a source/drain region of the lower FET to a first buried wire. Optionally, the metal components can also include second buried wire(s) in dielectric material at the same level as the upper FET and a second embedded contact that electrically connects a source/drain region of the upper FET to a second buried wire. Also disclosed are embodiments of a method of forming such IC structure embodiments.