Stacked Gate Crossing Layout for Low-Inductance Power Modules
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Solution Overview
Problem
Existing power semiconductor modules face challenges in achieving low gate path inductance, which is crucial for exploiting the fast switching capability of silicon carbide (SiC) devices, as high inductance can lead to voltage overshoots and potential device destruction.
Innovation Solution
A compact power semiconductor module design featuring a main substrate with stacked conductive layers and insulation layers, where power semiconductor chips are connected in parallel, and control conductors are arranged in a multilevel configuration to reduce inductance and increase power density, allowing for efficient gate signal distribution with low inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar gate path layouts are used, then the module structure is simple, but the gate path inductance is high causing voltage overshoots and potential device destruction
Solution Approach 1:
The patent transitions from a planar two-dimensional gate path layout to a three-dimensional stacked configuration. The gate paths are arranged in different vertical layers (first gate path in a first layer, second gate path in a second layer), with insulating layers separating these layers. This vertical stacking reduces the horizontal trace length and overlapping area between gate paths and commutation loops, thereby reducing gate path inductance and preventing voltage overshoots while maintaining structural integrity.
2Reliability
If larger module size is used to accommodate gate paths, then inductance can be reduced, but power density decreases
Solution Approach 1:
By stacking gate paths in vertical layers rather than spreading them horizontally, the patent reduces the overall footprint area required for the module. The insulating layers enable compact vertical integration of multiple gate paths, allowing the module to achieve low inductance performance without increasing planar dimensions, thereby maintaining high power density.
Solution Approach 2:
The patent nests multiple gate paths within a compact vertical structure. The first and second gate paths are nested in different layers, with each gate path surrounded by its own insulating layer and positioned above or below the other. This nested arrangement allows multiple functional paths to coexist in a small volume, achieving low inductance without sacrificing power density.
3Reliability
If gate paths are separated to reduce mutual inductance, then switching performance improves, but the module area increases
Solution Approach 1:
The patent separates gate paths in the vertical dimension rather than the horizontal dimension. The first gate path is positioned in a first layer and the second gate path in a second layer, with insulating layers providing electrical isolation. This vertical separation reduces mutual inductance between gate paths and commutation loops while maintaining a compact planar footprint, as the gate paths overlap in the horizontal projection but are isolated vertically.
Data Source
AI summary
A power semiconductor module includes a main substrate and power semiconductor chips. Each power semiconductor chip is bonded to the main conductive layer with the first power electrode. A first group of the power semiconductor chips is connected in parallel via the second power electrodes and a second group of the power semiconductor chips is connected in parallel via the second power electrodes. The module also includes a first insulation layer and a first conductive layer overlying the first insulation layer as well as a second insulation layer and a second conductive layer overlying the second insulation layer. The first conductive layer provides a first gate conductor area and a first auxiliary emitter conductor area for the first group. The second conductive layer provides a second gate conductor area and a second auxiliary emitter conductor area for the second group.