Stacked Gate Driver Circuit Layout Area Reduction
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Solution Overview
Problem
Display panels face challenges in minimizing the border area to maximize the display area, as the increasing number of wires in the non-display area occupies valuable space, and existing Gate Driver on Array (GOA) technology only partially addresses this issue.
Innovation Solution
The implementation of a display panel design with a gate driving area that includes a stack structure of a driving transistor and a driving storage capacitor, where the second electrode serves as both the gate electrode of the transistor and the top electrode of the capacitor, reducing the layout area and increasing capacitance and current density, allowing for a more compact gate driving circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of wires in the non-display area is increased to support more pixel units, then the display capability is improved, but the border area occupies more of the display area
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional stacked structure. The storage capacitor is positioned vertically above the transistor, utilizing the Z-dimension to reduce the footprint in the X-Y plane. This vertical stacking allows the gate driver circuit to occupy less border area while maintaining the same functional capability.
Solution Approach 2:
The storage capacitor is nested above the transistor in a vertical configuration. The capacitor's bottom electrode overlaps with the transistor's active area, and the capacitor structure is integrated within the same lateral footprint as the transistor, effectively nesting one component within the spatial envelope of another.
2Area of stationary object
If the gate driver circuit is integrated into the display area using GOA technology, then the border area is reduced, but the layout area of the gate driving circuit remains large
Solution Approach 1:
The patent employs vertical stacking to move the storage capacitor from the planar domain to the vertical domain. The capacitor is formed above the transistor with overlapping electrodes in the vertical direction, reducing the lateral layout area required for the gate driver circuit while maintaining integration within the display area.
Solution Approach 2:
The gate driver circuit components (transistor and storage capacitor) are merged into a single compact unit through vertical integration. The overlapping electrodes and shared dielectric layers combine the functions of both components within a reduced footprint, simplifying the overall layout of the gate driving circuit.
3Area of moving object
If the display area is increased to provide larger images, then the image size is improved, but the border area proportion increases
Solution Approach 1:
By stacking the storage capacitor vertically above the transistor, the patent reduces the lateral space required for the gate driver circuit. This vertical integration frees up border area that can be reallocated to expand the display area, thereby increasing the proportion of display area relative to the overall panel area.
Data Source
AI summary
A display panel having a display area and a gate driving area includes a gate line and plural pixel units in the display area, and a gate driver circuit in the gate driving area. The gate line connects to the pixel units. The gate driver circuit connects to the gate line. The gate driver includes a driving transistor and a driving storage capacitor stacked to each other to form a stack structure, which includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, a first semiconductor layer, a drain electrode, and a source electrode, which is connected to the gate line. The driving storage capacitor is formed by the first electrode, the first dielectric layer, and the second electrode. The driving transistor is formed by the second electrode, the second dielectric layer, the first semiconductor layer, the source electrode, and the drain electrode.