Stacked Gate Driver Layout for Narrow-Bezel Display Panels

The patent applies vertical stacking of transistors in different layers (moving from planar to three-dimensional arrangement) to reduce the horizontal non-display area. Multiple transistors are positioned at different vertical levels (first layer, second layer, third layer) to achieve higher density within the same footprint, directly resolving the contradiction between reducing area and managing manufacturing complexity.

The patent implements different crystallization conditions for transistors in different layers. Specifically, the first transistor is crystallized at a first temperature while the second transistor is crystallized at a second temperature different from the first. This local differentiation allows each layer to be optimized independently, managing the manufacturing complexity through controlled variation rather than uniform processing.

The patent changes the crystallization temperature parameter for transistors in different layers. The first transistor is crystallized at a first temperature, the second transistor at a second temperature, and the third transistor at a third temperature, with these temperatures being different from each other. This parameter variation enables optimization of operation characteristics for each transistor type while maintaining a systematic manufacturing approach.

The manufacturing process is segmented into distinct crystallization steps for different transistor layers. Rather than applying a single uniform crystallization process, the patent divides the process into multiple stages with different temperature conditions for different layers, making the complex manufacturing process more manageable through systematic segmentation.